CY2CC810OIT

COMLINK™ SERIES CY2CC810 1:10 Clock Fanout Buffer Features • • • • • • • • • • • • Low-voltage operation VDD range from 2.5V to 3.3V 1:10 fanout Over voltage tolerant input hot swappable Drives either a 50-Ohm or 75-Ohm transmission line Low-input capacitance Low-output skew Low-propagation delay Typical (tpd < 4 ns) High-speed operation > 500 MHz Industrial versions available Available packages include: SOIC, SSOP Description The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC810 fanout buffer features one input and ten outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. AVCMOS-type outputs dynamically adjust for variable impedance matching and eliminate the need for series damping resistors; they also reduce noise overall. Block Diagram Q1 Pin Configuration Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) IN GND Q1 VDD Q2 GND Q3 VDD Q4 GND CY2CC810 VD D IN INPUT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 GND 20 pin SOIC/SSOP Pin Description Pin Number 1 2, 6, 10, 13, 17 4, 8, 15, 20 3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Pin Name IN GND Input Ground Power Supply Output Description LVCMOS Power Power AVCMOS VDD Q1... Q10 Cypress Semiconductor Corporation Document #: 38-07056 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 COMLINK™ SERIES CY2CC810 Maximum Ratings[1][2] Storage Temperature: ................................–65°C to + 150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential VCC .................................................................. –0.5V to 4.6V Input ................................................................. –0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................... –0.5V to VDD + 1V DC Output Voltage.................................... –0.5V to VDD + 1V Power Dissipation........................................................ 0.75W DC Electrical Characteristics @ 3.3V (see Figure 5) Parameter Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V VDD = Min., VIN = VIH or VIL 80 –0.7 VIN = 2.7V VIN = 0.5V IOH = –12 mA IOL = 12 mA 2 Min. 2.3 Typ. 3.3 0.2 0.5 5.8 0.8 1 –1 20 –1.2 –50 100 Max. Unit V V V V uA uA uA V mA uA mV VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH DC Electrical Characteristics @ 2.5V (see Figure 1) Parameter Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 –0.7 VIN = 2.4V VIN = 0.5V IOH = –7 mA IOH = 12 mA IOL = 12 mA 1.6 Min. 1.8 1.6 0.65 5.0 0.8 1 –1 20 –1.2 –50 100 Typ. Max. Unit V V V V V uA uA uA V mA uA mV VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Capacitance Parameter Cin Cout Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Min. Typ. 2.5 6.5 Max. Unit pF pF Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07056 Rev. *C Page 2 of 7 COMLINK™ SERIES CY2CC810 Power Supply Characteristics (see Figure 5) Parameter ∆ICC ICCD IC Description Delta ICC Quiescent Power Supply Current Test Conditions (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD = Max. and VIN = VDD – 0.6V) Min. Typ. Max. 50 0.63 25 Unit uA mA/ MHz mA Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ High-frequency Parametrics Parameter DJ Description Jitter, Deterministic Test Conditions 50% duty cycle tW(50–50) The “point to point load circuit” Output Jitter – Input Jitter 50% duty cycle tW(50–50) Standard Load Circuit. 50% duty cycle tW(50–50) The “point to point load circuit” Fmax 2.5V Fmax(20) Maximum frequency VDD = 2.5 V Maximum frequency VDD = 3.3 V Maximum frequency VDD = 2.5 V tW Minimum pulse VDD = 3.3 V Minimum pulse VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V 20% duty cycle tW(20-80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 7 See Figure 7 See Figure 7 See Figure 5 Min. Typ. Max. 20 Unit ps Fmax Maximum frequency VDD = 3.3V 160 650 200 250 MHz MHz MHz See Figure 3 See Figure 7 1 200 MHz ns See Figure 3 1 AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 10 Pulse Skew: Skew between opposite transitions of the same output See Figure 9 (tPHL – tPLH). Package Skew: Skew between outputs of different packages at the See Figure 11 same power supply voltage, temperature and package type. Description See Figure 4 Min. 1.5 1.5 Typ. 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max. 3.5 3.5 Unit nS nS V/nS V/nS nS nS nS Document #: 38-07056 Rev. *C Page 3 of 7 COMLINK™ SERIES CY2CC810 AC Switching Characteristics @ 2.5V VDD = 2.5V ±5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay – Low to High Propagation Delay – High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 10 Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH). Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. See Figure 9 See Figure 11 Description See Figure 4 Min. Typ. Max. Unit 1.5 1.5 2.0 2.0 0.8 0.8 0.2 0.2 0.65 3.5 3.5 nS nS V/nS V/nS nS nS nS Parameter Measurement Information: VDD @ 2.5V From Output Under Test CL = 50 pF 500 ohm Parameter Measurement Information: VDD @ 3.3V From Output Under Test CL = 50 pF 500 ohm Figure 1. Load Circuit [3,4,5] Figure 5. Load Circuit [3,4,5] tw(50-50) Input 1.25 V tw(20-80) Input 1.25 V 1.25 V 2.0 V tw(50-50) Input 1.5V tw(20-80) Input 1.5V 1.5V 2.7V 0V 2.7V 0V 0V 2.0 V 0V Figure 2. Voltage Waveforms–Pulse Duration[6] Figure 6. Voltage Waveforms–Pulse Duration[6] From Output Under Test CL = 3 pF 500 ohm From Output Under Test CL = 3 pF 500 ohm Figure 3. Point to Point Load Circuit[3,4,5] Figure 7. Point to Point Load Circuit[3,4,5] Input tPLH Output 1.0 V 1.0 V tPHL 1.25 V 2.0 V 0V Input tPLH Output 1.5V 1.5V 1.5V tPHL 1.5V 2.7V 0V VOH 1.25 V VOL VOH VOL Figure 4. Voltage Waveforms– Propagation Delay Times[4] Figure 8. Voltage Waveforms– Propagation Delay Times[4] Notes: 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50W, tR < 2.5 nS, tF < 2.5 nS. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd. Document #: 38-07056 Rev. *C Page 4 of 7 COMLINK™ SERIES CY2CC810 3V 1.5V INPUT tPLH tPHL 0V VOH 1.5V OUTPUT tsk (P) = VOL l tPHL - tPLH l 3V 1 .5 V Figure 9. Pulse Skew–tsk(p) IN P U T tP L H 1 tP H L 1 0V VOH 1 .5 V OUTPUT 1 ts k (O ) tsk (O ) VOL VOH 1 .5 V OUTPUT 2 VOL tP L H 2 tP L H 2 ts k (P ) = l t P LH 2 - t P L H 1 l o r t P H L 2 - t P H L1 l 3V 1.5V Figure 10. Output Skew–tsk(0) INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk (t) tsk (t) VOL VOH 1.5V P ACKAGE 2 OUTPUT VOL tPLH 2 tPLH 2 tsk (t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 11. Package Skew–tsk(t) Ordering Information Part Number CY2CC810SI CY2CC810SIT CY2CC810OI CY2CC810OIT CY2CC810SC CY2CC810SCT CY2CC810OC CY2CC810OCT Package Type 20-pin SOIC 20-pin SOIC–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel 20-pin SOIC 20-pin SOIC–Tape and Reel 20-pin SSOP 20-pin SSOP–Tape and Reel Product Flow Industrial, –40°C to 85°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Document #: 38-07056 Rev. *C Page 5 of 7 COMLINK™ SERIES CY2CC810 Package Drawing and Dimensions 20-lead (300-mil) Molded SOIC S5 51-85024-A 20-lead (5.3-mm) Shrunk Small Outline Package O20 51-85077-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07056 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINK™ SERIES CY2CC810 Document History Page Document Title: CY2CC810 1:10 Clock Fanout Buffer Document #: 38-07056 REV. ** *A *B ECN NO. 107081 114315 119117 Issue Date 06/07/01 05/09/02 10/07/02 Orig. of Change IKA TSM RGL ∆ IDD Validation Added 5.8 as the Max. value of VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 1.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Added power up requirements to maximum ratings information. Description of Change Convert from IMI to Cypress *C 122743 12/14/02 RBI Document #: 38-07056 Rev. *C Page 7 of 7