CY2DP314OIT

CY2DP314 1:4 Differential Clock/Data Fanout Buffer Features • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs (CLKA) • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable • 29 ps typical output-to-output skew • 95 ps typical part-to-part skew • 400 ps typical propagation delay • 0.16 ps typical RMS phase jitter • 7 ps typical peak period jitter • 1.5-GHz operation (2.7-GHz maximum toggle frequency) • PECL and HSTL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 20-pin SSOP package • Temperature compensation like 100K ECL Functional Description The CY2DP314 is a low-skew, low propagation delay 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz (full swing). The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP314 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL or LVCMOS /LVTTL single-ended signal to four ECL/PECL differential loads. Since the CY2DP314 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP314 delivers consistent performance over various platforms. Block Diagram VCC CLKA CLKA# Q0 Q0# Pin Configuration VCC NC VCC CLK_SEL CLKA CLKA# CLKB CLKB# VEE VCC CY2DP314 Q1 Q1# VEE VCC CLKB CLKB# Q2 Q2# VEE CLK_SEL Q3 Q3# 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q0# Q1 Q1# Q2 Q2# Q3 Q3# VCC 20-pin SSOP VEE Cypress Semiconductor Corporation Document #: 38-07550 Rev.*G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 22, 2005 CY2DP314 Pin Definitions Pin 1,10,11,20,3 2 4 5 6 7 8 9 18,16,14,12 19,17,15,13 Table 1. Control CLK_SEL 0 1 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations CLKB, CLKB# input pair is active. CLKB can be driven with HSTL-compatible signals with respective power configurations Operation NC CLK_SEL CLKA CLKA# CLKB CLKB# VEE[2] Q[0:3]# Q[0:3] I,PD I,PD[1] I, PD/PU I,PD I, PD/PU –PWR O O ECL/PECL ECL/PECL ECL/PECL HSTL HSTL Power ECL/PECL ECL/PECL Name VCC I/O +PWR Type Power No connect Input Clock Select Default differential clock input Default differential clock input Alternate differential clock input Alternate differential clock input Power supply, negative connection Complement output True output Description Power supply, positive connection Governing Agencies The following agencies provide specifications that apply to the CY2DP314. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name JEDEC Specification JESD 020B (MSL) JESD 8-6 (HSTL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) 883E Method 1012.1 (Thermal Theta JC) Mil-Spec Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power. 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. Document #: 38-07550 Rev.*G Page 2 of 10 CY2DP314 Absolute Maximum Ratings Parameter VCC VEE TS TJ ESDh MSL Description Positive Supply Voltage Negative Supply Voltage Temperature, Storage Temperature, Junction ESD Protection Moisture Sensitivity Level Assembled Die Condition Non-Functional Non-Functional Non-Functional Non-Functional Human Body Model 2000 3 50 Min. –0.3 -4.6 –65 Max. 4.6 0.3 +150 150 Unit V V °C °C V N.A. gates Gate Count Total Number of Used Gates Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter LUI TA ØJc ØJa IEE CIN LIN VIN VTT VOUT IIN Description Latch Up Immunity Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient Maximum Quiescent Supply Current Input pin capacitance Pin Inductance Input Voltage Output Termination Voltage Output Voltage Input Current[6] Relative to VCC[5] Relative to VCC [5] Condition Functional, typical Functional Functional Functional VEE pin Min. 100 –40 37[3] 132[3] Max. +85 Unit mA °C °C/W °C/W 130[4] 3 1 –0.3 –0.3 VCC + 0.3 VCC – 2 VCC + 0.3 l150l mA pF nH V V V uA Relative to VCC[5] VIN = VIL, or VIN = VIH PECL/HSTL DC Electrical Specifications Parameter VCC VCMR VX VOH VOL VIH Description Operating Voltage PECL Input Differential Crosspoint Voltage[7] HSTL Input Differential Crosspoint Voltage[8] Output High Voltage Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% Input Voltage, High Condition 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V Differential operation Standard Load Differential Operation IOH = –30 mA[9] IOL = –5 mA[9] Min. 2.375 3.135 1.2 0.68 VCC – 1.25 VCC – 1.995 VCC –1.995 VCC – 1.165 1.945[10] Max. 2.625 3.465 VCC 0.9 VCC – 0.7 VCC – 1.5 VCC – 1.3 VCC – 0.880[10] Unit V V V V V V V V Single-ended operation VIL Input Voltage, Low Single-ended operation VCC – VCC – 1.625 V Notes: 3. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1. 4. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 5. where VCC is 3.3V±5% or 2.5V±5%. 6. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 7. Refer to Figure 1. 8. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Figure 2. 9. Equivalent to a termination of 50Ω to VTT. IOHMIN = (VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50. 10. VIL will operate down to VEE; VIH will operate up to VCC. Document #: 38-07550 Rev.*G Page 3 of 10 CY2DP314 ECL DC Electrical Specifications Parameter VEE VCMR VOH VOL VIH VIL Description Negative Power Supply ECL Input Differential cross point voltage[7] Output High Voltage Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% Input Voltage, High Input Voltage, Low Condition –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V Differential operation IOH = –30 mA[9] IOL = –5 mA[9] Single-ended operation Single-ended operation Min. –2.625 –3.465 VEE + 1.2 –1.25 –1.995 –1.995 –1.165 –1.945[10] Max. –2.375 –3.135 0V –0.7 –1.5 –1.3 –0.880[10] –1.625 Unit V V V V V V AC Electrical Specifications Parameter VPP VCMRO FCLK TPD VDIF VX Vo tsk(0) tsk(PP) tjit(per) tjit(pn) Description ECL/PECL Input Differential Input Voltage[7] Output Common Voltage Range Input Frequency Propagation Delay CLKA or CLKB to Output pair[12] HSTL Differential Input Voltage[11] HSTL Input Differential Crosspoint Voltage[8] Output Voltage (peak-to-peak; see Figure 2) Output-to-output Skew Part-to-Part Output Output Period Jitter Skew[12] (peak)[13] 156.25 MHz[12] 156.25 MHz, broadband, 3.3V 156.25 MHz, Filtered, 3.3V 312.5 MHz, broadband, 3.3V 312.5 MHz, Filtered, 3.3V tsk(P) TR,TF Output Pulse Skew[14] Output Rise/Fall Time (see Figure 2) 660 MHz[12], See Figure 3 50% duty cycle Differential 20% to 80% 50% duty cycle Standard load PECL, ECL < 660 MHz HSTL < 1 GHz Duty Cycle Standard Load Differential Operation Standard Load Differential Operation < 1 GHz = 0 .4 V m in V X m a x = 0 .9 V V D IF VX V IL VEE V E E = 0 .0 V V X M in = 0 .6 8 Figure 2. HSTL Differential Input Waveform Definitions tr, tf, 2 0 -8 0 % VO Figure 3. ECL/LVPECL Output In p u t C lo c k VPP TPLH, TPD O u tp u t C lo c k TPHL VO tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07550 Rev.*G Page 5 of 10 CY2DP314 Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT R T = 50 ohm P u ls e G e n e ra to r Z = 50 ohm 5" VTT R T = 50 ohm Zo = 50 ohm R T = 50 ohm VTT DUT C Y2D P314 Zo = 50 ohm 5" R T = 50 ohm VTT Figure 5. CY2DP314 AC Test Reference Supplemental Parametric Information RMS Phase Jitter: 0.159 ps typical @ 156.25 MHz, 10 GbE Filter (1.875 MHz – 20 MHz) 0.175 ps typical @ 156.25 MHz, Broadband (Raw Data from 10 Hz – 20 MHz) 0 -20 10 GbE Filter SSB Phase-noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 -180 -200 10 Hz 1.E+01 100 Hz 1.E+02 1 KHz 1.E+03 10 KHz 1.E+04 100 KHz 1.E+05 1 MHz 1.E+06 10 MHz 1.E+07 100 MHz 1.E+08 Raw Phase Noise Data Raw Data plus 10 GbE Filter Offset Frequency (Hz) Figure 6. Typical Phase-noise Characteristics at 156.25 MHz, 3.3V, Room Temperature Document #: 38-07550 Rev.*G Page 6 of 10 CY2DP314 Applications Information Termination Examples CY2DP314 VCC 5" VTT R T = 50 ohm Zo = 50 ohm 5" R VTT T = 50 ohm VEE Figure 7. Standard LVPECL – PECL Output Termination CY2DP314 VCC 5" VTT R T = 50 ohm Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 8. Driving a PECL/ECL Single-ended Input CY2DP314 V C C = 3 .3 V 5" 3 .3 V 120 ohm LVDS Zo = 50 ohm 5" 33 ohm ( 2 p la c e s ) 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) VEE = 0V L V P E C L to LVDS Figure 9. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface Document #: 38-07550 Rev.*G Page 7 of 10 CY2DP314 VDD-2 X VCC Y Z One output is shown for clarity Figure 10. Termination for LVPECL to HTSL interface for VCC = 2.5V would use X = 50 Ohms, Y = 2300 Ohms, and Z = 1000 Ohms. See application note titled PECL Translation, SAW Oscillators, and Specs for Other Signalling Standards and Supplies Ordering Information Part Number CY2DP314OI CY2DP314OIT Lead-free CY2DP314OXI CY2DP314OXIT 20-pin SSOP 20-pin SSOP – Tape and Reel Industrial, –40° to 85°C Industrial, –40° to 85°C Package Type 20-pin SSOP 20-pin SSOP – Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Document #: 38-07550 Rev.*G Page 8 of 10 CY2DP314 Package Drawing and Dimensions 20-Lead (5.3 mm) Shrunk Small Outline Package O20 51-85077-*C FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07550 Rev.*G Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2DP314 Document History Page Document Title: CY2DP314 FastEdge SERIES 1:4 Differential Clock/Data Fanout Buffer Document Number: 38-07550 REV. ** *A ECN NO. Issue Date 126779 128940 06/13/03 08/19/03 Orig. of Change RGL RGL New data sheet Changed the operation value from 1.5 GHz, reduced swing to 3 GHz to from DC to above 1.5 GHz Changed VCC value in the IIN parameter from 3.6V to 3.645V. Changed the VOL min value from VCC–1.9 to VCC–1.945 Changed the IEE max value from 48 mA to 130 mA Specified the max input frequency (FCLK) to 2200 MHz Specified the TTB max value to 250 ps Added Junction Temperature (TJ) parameter in the Absolute Max. Conditions table Replaced ICC calculation with power calculation in the footnote Provided data for TBDs to match the device Description of Change *B *C *D *E *F *G 207710 237748 247603 270151 346157 393406 See ECN See ECN See ECN See ECN See ECN See ECN RGL RGL RGL/GGK Changed VOH and VOL to match the Char Data RGL Removed all VBB references Added Lead-free devices RGL RGL Minor Change: corrected the CLK_SEL input type to ECL/PECL Updated Jitter values, Added typical values Document #: 38-07550 Rev.*G Page 10 of 10