CY2DP814_08

CY2DP814 1:4 Clock Fanout Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output pairs. Designed for data communications clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DP814 is ideal for both level translations from single-ended to LVPECL, and/or for the distribution of LVDS-based clock signals. The Cypress CY2DP814 has configurable input between logic families. The input can be selectable for an LVPECL, LVTTL or LVDS signal, while the output drivers support LVPECL capable of driving 50-ohm lines. Low-voltage operation VDD = 3.3V 1:4 fanout Single input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVPECL outputs Drives 50-ohm load Low input capacitance Less than 4 ns typical propagation delay 85 ps typical output-to-output skew Industrial versions available Available in TSSOP package Logic Block Diagram EN1 1 EN2 8 16 Q1A 15 Q1B 14 Q2A 13 Q2B IN+ 6 IN- 7 LVDS / LVPECL / LVTTL CONFIG 2 12 Q3A 11 Q3B 10 Q4A 9 Q4B OUTPUT LVPECL Cypress Semiconductor Corporation Document #: 38-07060 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 22, 2008 [+] [+] Feedback CY2DP814 Pin Configuration Figure 1. 16-Pin TSSOP/SOIC EN1 CONFIG VDD VDD GND IN+ INEN2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B 16 pin TSSOP / SOIC Pin Description Pin Number 6, 7 2 Pin Name IN+, IN– CONFIG Pin Standard Interface Configurable LVTTL/LVCMOS Description Differential input pair or single line. LVPECL default. See CONFIG below. Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1). See Figure 6 and Figure 7 for additional information Enable/disable logic. See Function Table below for details. Differential outputs. 1, 8 16, 15, 14, 13, 12, 11, 10, 9 EN1, EN2 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B VDD GND LVTTL/LVCMOS LVPECL 3, 4 5 POWER POWER CY2DP814 Positive supply voltage. Ground. Document #: 38-07060 Rev. *E Page 2 of 9 [+] [+] Feedback CY2DP814 Maximum Ratings[1, 2] Storage Temperature: ................................. –65°C to +150°C Ambient Temperature: .................................. –40°C to +85°C Supply Voltage to Ground Potential (Inputs and VCC only) .......................................–0.3V to 4.6V Table 1. EN1 EN2 Function Table Enable Logic EN1 H H L L CONFIG Pin 2 Binary Value 1 0 EN2 H L L H IN+ H H H X Input Receiver Family LVTTL in LVCMOS LVDS LVPECL Input Supply Voltage to Ground Potential (Outputs only) ........................................ –0.3V to VDD + 0.3V DC Input Voltage ................................... –0.3V to VDD + 0.3V DC Output Voltage................................. –0.3V to VDD + 0.9V Power Dissipation........................................................ 0.75W Outputs IN– L L L X QnA H H H Z Input Receiver Type QnB L L L Z Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS Single ended, non-inverting, inverting, void of bias resistors. Low voltage differential signaling Low voltage pseudo (positive) emitter coupled logic LVTTL/LVCMOS INPUT LOGIC Input Logic Input Input Input Input Test Conditions Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal Input Condition IN– Pin 7 IN+ Pin 6 IN– Pin 7 IN+ Pin 6 IN+ Pin 6 IN– Pin 7 IN+ Pin 6 IN– Pin 7 Description Output Logic Q pins True Invert Invert True Min Typ 1.5 90 Max 2.0 100 Unit mA/MHz mA Ground VCC Ground VCC Table 4. Power Supply Characteristics Parameter ICCD IC Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Loaded, fL= 100 MHz Conditions Table 5. DC Electrical Characteristics: 3.3V–LVDS Input Parameter VID VIC IIH IIL II Description Magnitude of Differential Input Voltage Common-Mode of Differential Input Voltage IVIDI (min. and max.) Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VIN = VDD VIN = VSS Min 100 IVIDI /2 Typ Max Unit 600 mV 2.4– (IVIDI /2) ±10 ±0 ±20 ±20 ±20 V μA μA μA Notes 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07060 Rev. *E Page 3 of 9 [+] [+] Feedback CY2DP814 Table 6. DC Electrical Characteristics: 3.3V–LVPECL Input Parameter I VID I Description Differential Input Voltage p-p Common-mode Voltage Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. Condition Guaranteed Logic High Level VIN = VDD VIN = VSS Min 400 1650 Typ Max 2600 2250 Unit mV mV μA μA μA VCM IIH IIL II ±10 ±10 ±20 ±20 ±20 VDD = Max., VIN = VDD(max.) Table 7. DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input Parameter VIH VIL IIH IIL II VIK VH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Condition Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VDD = Min., IIN = –18 mA –0.7 80 VIN = 2.7V VIN = 0.5V Min 2 0.8 1 –1 20 –1.2 Typ Max Unit V V μA μA μA V mV Table 8. DC Electrical Characteristics: 3.3V–LVPECL Output Parameter I VOD I I VOC I Rise Time Fall Time VOH VOL IOS Output High Voltage Output Low Voltage Short Circuit Current Description Driver Differential Output Voltage p-p Driver common-mode p-p Differential 20% to 80% Condition VDD = Min., VIN = VIH or VIL RL = 50 ohm VDD = Min., VIN = VIH or VIL RL = 50 ohm CL–10 pF RL and CL to GND User-defined (see Figure 1) VDD = Max., VOUT = GND RL = 50 ohm Min 1000 – 300 2.1 – –125 – – – –150 Typ – – Max 3600 226 800 3.0 Unit mV mV ps V V mA VDD = Min., VIN = VIH or VIL IOH = –12 mA Table 9. AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C Parameter tPLH tPHL tPD tPE Tpd tSK(0) tSK(p) tSK(t) Description Propagation Delay—Low to High Propagation Delay—High to Low Propagation Delay Enable (EN) to functional operation Functional operation to Disable Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) Package Skew: Skew between outputs of different packages at the VID = 100 mV same power supply voltage, temperature and package type. Same input signal level and output load. Conditions VOD = 100 mV Min 3 3 3 – – – – – Typ 4 4 4 – – 0.085 0.2 – Max 5 5 5 6 5 0.2 – 1 Unit ns ns ns ns ns ns ns ns IN [+,–] to Q[A,B] Data & Clock Speed EN [1,2] to Q[A,B] Control Speed Document #: 38-07060 Rev. *E Page 4 of 9 [+] [+] Feedback CY2DP814 Figure 2. Differential PECL Output VDD VDD - 2V Q Q Device concept User Defined VTT & RTT Table 10. High-frequency Parametrics Parameter Fmax Fmax(20) Description Maximum Frequency VDD = 3.3V Maximum Frequency VDD = 3.3V Minimum Pulse VDD = 3.3V Conditions 50% Duty Cycle tW(50–50) Standard Load Circuit 20% Duty Cycle tW(20–80) LVPECL Input Vin = VIH(Max.)/VIL(Min.) Vout = VOH(Min.)/VOL (Max.) (Limit) LVPECL Input Vin = VIH(Max.)/VIL(Min.) F = 100 MHz Vout = VOH(Min.)/VOL(Max.).(Limit) 900 Min Typ Max 450 175 Unit MHz MHz TW ps Figure 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6, 7] A P ulse G enera tor T PA 150 B 150 GND 10pF 50 TPC V D D -2V 50 T PB E n1 E n2 S tan dard T erm in ation V 1A V 1B 1 .2 V C M 1.4 V 0 V D if f e r e n t ia l 1.0 V 1.4 V V 0Y 1 .2 V C M 0 V D if f e r e n t ia l V 0Z T PLH TPHL 1.0 V V0Y V0Z t R t F 80% 0 V D if f e r e n t ia l 20% Notes 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6 = Ó. 4. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 5. TPA and B are used for prop delay and rise/fall measurements. TPC is used for VOC measurements only and otherwise connected to VDD – 2. 6. When measuring Tr/Tf, tpd, VOD point TPC is held at VDD – 2.0V. 7. LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the complement of the input on B side. See Table 3. Document #: 38-07060 Rev. *E Page 5 of 9 [+] [+] Feedback CY2DP814 Figure 4. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 7, 8] A P u ls e G e n e ra to r TPA 150 B 150 GND 50 TPC 50 TPB En1 En2 VOC VOD S ta n d a rd T e rm in a tio n V I(A ) V I(B ) 1 .4 V 1 .0 V V o c (p p ) VDD V o c (s s ) Figure 5. Test Circuit and Voltage Definitions for the Differential Output Signal [3, 4, 5, 6, 7] A Pulse Generator TPA 150 B 150 GND 10pF 50 TPC VDD-2V 50 TPB En1 En2 Standard Termination VI(A) VI(B) 1.4V 1.0V 100% 80% 0.0V 20% 0% tF tR Document #: 38-07060 Rev. *E Page 6 of 9 [+] [+] Feedback CY2DP814 Figure 6. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[3, 4, 5, 8, 9] P uls e G en era to r P uls e G e nerator VOC TPA 50 TPC VDD-2V 50 TPB En1 En2 + DE Parallel Termination Q tpd Figure 7. LVTTL/LVCMOS tpe Figure 8. LVDS/LVPECL INPUT A LVCM OS / LVTTL INPUT B GND LVPECL & LVDS In C o n fig InConfig 1 0 L V D S /L V P E C L LVTTL/LVCMOS Ordering Information Part Number CY2DP814ZCT Package Type 16-pin TSSOP–Tape and Reel 16-pin TSSOP 16-pin TSSOP–Tape and Reel 16-pin TSSOP 16-pin TSSOP–Tape and Reel Product Flow Commercial, 0°C to 70 °C Commercial, 0°C to 70 °C Commercial, 0°C to 70 °C Industrial, –40°C to 85 °C Industrial, –40°C to 85 °C Pb free CY2DP814ZXC CY2DP814ZXCT CY2DP814ZXI CY2DP814ZXIT Notes 8. VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz. 9. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF < 1 ns; pulse re-rate = 50 Mpps; pulse width = 10 ± 0.2 ns. Document #: 38-07060 Rev. *E Page 7 of 9 [+] [+] Feedback CY2DP814 Package Drawing and Dimensions Figure 9. 16-Pin TSSOP 4.40 mm Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 51-85091-*A 4.90[0.193] 5.10[0.200] 0.09[[0.003] 0.20[0.008] Note 10. LVPECL or LVDS differential input value. Document #: 38-07060 Rev. *E Page 8 of 9 [+] [+] Feedback CY2DP814 Document History Page Document Title: CY2DP814 1:4 Clock Fanout Buffer Document Number: 38-07060 REV. ** *A *B *C ECN No. 10785 115610 122746 382376 Submission Date 06/07/01 07/02/02 12/15/02 See ECN Orig. of Change IKA CTK RBI RGL Range of VCM Description of Change Convert from IMI to Cypress Added power-up requirements to maximum ratings information. Added Lead-free device for TSSOP commercial Removed pruned parts Added typical values Added Lead-free for TSSOP Industrial Removed CY2DP814ZC from the Ordering Information Updated template *D *E 403374 2595534 See ECN 10/23/08 RGL CXQ Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2005-2008. 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Document #: 38-07060 Rev. *E All products and company names mentioned in this document may be the trademarks of their respective holders. Revised October 22, 2008 Page 9 of 9 [+] [+] Feedback