CY2PP326

FastEdge™ Series CY2PP326 2 x 2 Clock and Data Switch Buffer Features • Six ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 250 ps device-to-device skew • 950 ps propagation delay (typical) • 1.2 GHz Operation • 2.8 ps RMS period jitter (max.) • PECL mode supply range: VEE = –2.5V± 5% to –3.3V±5% with VEE = 0V • ECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • Industrial temperature range: –40°C to 85°C • 32-pin 1.4mm TQFP package • Temperature compensation like 100K ECL • Pin Compatible with MC100ES6254 Functional Description The CY2PP326 is a low-skew, low propagation delay 2 x 2 differential clock, data switch, and fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths which are multiplexed internally to six outputs grouped in two banks. The muxes are controlled by SEL(0:1) control inputs. The CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and as a clock/data repeater or multiplexer. Since the CY2PP326 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems and for switching data signals between different channels. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP326 delivers consistent, guaranteed performance over differing platforms. Block Diagram VCC CLK0 CLK0# VEE VCC 0 1 Pin Configuration Bank A QA0# QA1# QA2# VCC VCC QA0 QA1 QA1 QA1# QA2 QA2# VCC VEE SEL1 CLK1 CLK1# OEB# VEE VCC 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 QA2 QA0 QA0# VCC VEE OEA# CLK0 CLK0# SEL0 VEE VCC B ank B CLK1 CLK1# VEE 0 1 Q B0 Q B0# Q B1 Q B1# Q B2 Q B2# CY2PP326 21 20 19 18 17 SEL0 SEL1 VEE O EA# O EB# VEE Sync 9 QB0# 10 11 12 13 14 15 16 VCC QB1# VCC QB0 QB1 QB2# QB2 Cypress Semiconductor Corporation Document #: 38-07506 Rev.*D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2004 FastEdge™ Series CY2PP326 Pin Definitions Pin 19,3 22,6 21,4 20,5 31,28,25 32,29,26 10,13,16 9,12,15 2,7,18,23, 1,8,11,14,17,24,27,30 Table 1. Function Table Control OAE# Default 0 0 1 QA(0–2), QX(0–2)# are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can can be asynchronous to the reference clock without be asynchronous to the reference clock without generation of output runt pulses. generation of output runt pulses. QA(0–2), QX(0–2)are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can can be asynchronous to the reference clock without be asynchronous to the reference clock without generation of output runt pulses. generation of output runt pulses. See Table 2 Name SEL0,SEL1 OEA#,OEB# CLK(0:1) CLK(0:1)# QA(0:2) QA(0:2)# QB(0:2) QB(0:2)# VEE VCC I/O[1] I I I,PD I,PD/PU O O –PWR +PWR Type[2] LVCMOS LVCMOS Output Enable. Description Clock/Data Switch Select. ECL/PECL True Differential Inputs. ECL/PECL Complement Differential Inputs. ECL/PECL Differential Outputs – Bank A. ECL/PECL Differential Outputs – Bank B. GND POWER Negative Power Supply. Positive Power Supply. OEB# 0 SEL0,SEL1 00 Table 2. Clock Select Control SEL0 0 0 1 1 SEL1 0 1 0 1 CLK0 Routed to QA(0:2) and QB(0:2) – QA(0:2) QB(0:2) CLK1 Routed to – QA(0:2) and QB(0:2) QB(0:2) QA(0:2) Application Mode 1:6 fanout of CLK0 1:6 fanout of CLK1 Dual 1:3 buffer Dual 1:3 buffer crossed Governing Agencies The following agencies provide specifications that apply to the CY2PP326. The agency name and relevant specification is listed below in Table 3. Table 3. Agency Name JEDEC Specification JESD 020B (MSL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) 883E Method 1012.1 (Thermal Theta JC) Mil-Spec Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. Document #: 38-07506 Rev.*D Page 2 of 9 FastEdge™ Series CY2PP326 Absolute Maximum Ratings Parameter VCC VEE TS TJ ESDh MSL Description Positive Supply Voltage Negative Supply Voltage Temperature, Storage Temperature, Junction ESD Protection Moisture Sensitivity Level Assembled Die Condition Non-Functional Non-Functional Non-Functional Non-Functional Human Body Model 2000 3 50 Min. –0.3 -4.6 –65 Max. 4.6 0.3 +150 150 Unit V V °C °C V N.A. gates Gate Count Total Number of Used Gates Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter LUI TA ØJc ØJa IEE CIN LIN VIN VTT VOUT IIN Description Latch Up Immunity Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient Maximum Quiescent Supply Current Input pin capacitance Pin Inductance Input Voltage Output Termination Voltage Output Voltage Input Current[6] Relative to VCC[5] Relative to VCC[5] Relative to VCC[5] VIN = VIL, or VIN = VIH –0.3 –0.3 VCC – 2 VCC + 0.3 l150l Condition Functional, typical Functional Functional Functional VEE pin –40 29[3] 75[3] 130 [4] 3 1 VCC + 0.3 Min. 100 +85 Max. Unit mA °C °C/W °C/W mA pF nH V V V uA PECL DC Electrical Specifications Parameter VCC VCMR VOH VOL VIH VIL Description Operating Voltage Differential Cross Point Voltage[7] Output High Voltage Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% Input Voltage, High Input Voltage, Low Condition 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V Differential operation IOH = –30 mA [8] Min. 2.375 3.135 1.2 VCC – 1.25 VCC – 1.995 VCC –1.995 VCC – 1.165 VCC – 1.945 [9] Max. 2.625 3.465 VCC VCC – 0.7 VCC – 1.5 VCC – 1.3 VCC – 0.880 [9] VCC – 1.625 Unit V V V V V V V V IOL = –5 mA[8] Single-ended operation Single-ended operation Notes: 3. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 4. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 5. where VCC is 3.3V±5% or 2.5V±5% 6. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 7. Refer to Figure 1 8. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 9. VIL will operate down to VEE; VIH will operate up to VCC Document #: 38-07506 Rev.*D Page 3 of 9 FastEdge™ Series CY2PP326 ECL DC Electrical Specifications Parameter VEE VCMR VOH VOL VIH VIL Description Negative Power Supply Differential cross point voltage[7] Output High Voltage Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% Input Voltage, High Input Voltage, Low Condition –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V Differential operation IOH = –30 mA[8] IOL = –5 mA[8] Single-ended operation Single-ended operation Min. –2.625 –3.465 VEE + 1.2 –1.25 –1.995 –1.995 –1.165 –1.945 [9] Max. –2.375 –3.135 0V –0.7 –1.5 –1.3 –0.880 [9] –1.625 Unit V V V V V V AC Electrical Specifications Parameter VPP FCLK TPD Vo VCMRO tsk(0) tsk(PP) TPER tsk(P) TR,TF tPDL tPLD Description Differential Input Voltage[7] Input Frequency Propagation Delay CLKA or CLKB to Output pair Condition Differential operation 50% duty cycle Standard load < 1 GHz [10] Min. 0.1 – – 0.375 Max. 1.3 1.5 1200 – Unit V GHz ps V V Output Voltage (peak-to-peak; see Fig- < 1 GHz ure 2) Output Common Voltage Range (typ.) Output-to-output Skew Part-to-Part Output Skew Output Period Jitter (rms)[11] Output Pulse Skew[12] 660 MHz [10], VCC – 1.425 See Figure 3 – – – – 0.08 2.5T + TPD 3.0T + TPD S p litte r O p tio n s S E L 0 /1 C L K 0 /0 # Bank A 50 250 2.8 75 0.3 3.5T + TPD 4.0T + TPD ps ps ps ps ns ns ns 660 MHz [10] 660 MHz [10] 660 MHz [10], See Figure 3 660 MHz 50% duty cycle Differential 20% to 80% T = CLK period T = CLK period Output Rise/Fall Time (see Figure 2) Output disable time Output enable time R o u te r O p tio n s S E L 0 /1 C L K 0 /0 # Bank A C L K 1 /1 # Bank B C L K 1 /1 # Bank B S w itc h S p litte r A C L K 0 /0 # Bank A C L K 0 /0 # Bank A C L K 1 /1 # Bank B C L K 1 /1 # Bank B S E L 0 /1 R e p e a te r S p litte r B S E L 0 /1 Figure 1. Channel Cross Point Switch/Mux Configurations Notes: 10. 50% duty cycle; standard load; differential operation 11. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points 12. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07506 Rev.*D Page 4 of 9 FastEdge™ Series CY2PP326 Timing Definitions VCC VCM R Max = VCC V IH VPP VPP range 0.1V - 1.3V VCM R VIL VCMR M in = VEE + 1.2 VEE Figure 2. PECL/ECL Input Waveform Definitions tr, tf, 20-80% VO Figure 3. ECL/LVPECL Output In p u t C lo c k VPP TPLH, TPD O u tp u t C lo c k TPHL VO tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07506 Rev.*D Page 5 of 9 FastEdge™ Series CY2PP326 CLKX CLKX 1 2 3 1 2 3 50% OEX tPDL(OE[X] to Q[X} tPLD(OE[X] to Q[X} Q[X] Q[X]# Figure 5. Output Disable/Enable Timing Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT RT = 50 ohm P u ls e G e n e ra to r Z = 50 ohm 5" VTT RT = 50 ohm Zo = 50 ohm RT = 50 ohm VTT DUT C Y2PP326 Zo = 50 ohm 5" RT = 50 ohm VTT Figure 6. CY2PP326 AC Test Reference Applications Information Termination Examples CY2PP326 VCC 5" VTT RT = 50 ohm Zo = 50 ohm 5" RT = 50 ohm VTT VEE Figure 7. Standard LVPECL – PECL Output Termination Document #: 38-07506 Rev.*D Page 6 of 9 FastEdge™ Series CY2PP326 CY2PP326 VCC 5" VTT RT = 50 ohm Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 8. Driving a PECL/ECL Single-ended Input CY2PP326 V C C = 3 .3 V 5" 3 .3 V 120 ohm LVDS Zo = 50 ohm 5" 33 ohm ( 2 p la c e s ) 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) VEE = 0V L V P E C L to LVDS Figure 9. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface VDD-2 X VCC Y Z One output is shown for clarity Figure 10. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and supplies. Ordering Information Part Number CY2PP326AI CY2PP326AIT 32-pin TQFP 32-pin TQFP – Tape and Reel Package Type Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Document #: 38-07506 Rev.*D Page 7 of 9 FastEdge™ Series CY2PP326 Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 Dimensions in mm. 51-85088-*B FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07506 Rev.*D Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FastEdge™ Series CY2PP326 Document History Page Document Title: CY2PP326 FastEdge™ Series 2 x 2 Clock and Data Switch Buffer Document Number: 38-07506 REV. ** *A ECN NO. 122361 129269 Issue Date 02/12/03 09/09/03 Orig. of Change RGL RGL New Data Sheet Changed ComLink to FastEdge Added tPLDg and tPDLf specs in the AC specs table Added the Output disable/enabling timing diagram Deleted the output reference voltage in the absolute max. conditions Fixed the AC/DC Electrical specs to match the EROS Posted to external web Supplied data to all TBD’s to match the device. Description of Change *B *C *D 131346 237751 247620 11/20/03 See ECN See ECN RGL RGL RGL/GGK Changed VOH and VOL to match the Char Data Document #: 38-07506 Rev.*D Page 9 of 9