CY2SSTV850ZC

STV850 CY2SSTV850 Differential Clock Buffer/Driver Features • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:10 differential outputs • External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for EMI reduction • 48-pin SSOP and TSSOP packages • Conforms to JEDEC JC40 and JC42.5 DDR specifications Description This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram Pin Configuration 10 YT0 YC0 YT1 YC1 YT2 YC2 SCLK SDATA Serial Interface Logic YT4 YC4 YT5 YC5 YT6 YC6 CLKINT CLKINC PLL FBINT FBINC YT7 YC7 YT8 YC8 YT9 YC9 CY2SSTV850 YT3 YC3 AVDD FBOUTT FBOUTC VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKINT CLKINC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS YC5 YT5 VDDQ YT6 YC6 VSS VSS YC7 YT7 VDDQ SDATA FBINT FBINC VDDQ FBOUTC FBOUTT VSS YC8 YT8 VDDQ YT9 YC9 VSS Cypress Semiconductor Corporation Document #: 38-07457 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 18, 2001 CY2SSTV850 Pin Description[1, 2] Pin 13 14 35 36 3, 5, 10, 20, 22 46, 44, 39, 29,27 2, 6, 9, 19, 23 47, 43, 40,30,26 32 Name CLKINT CLKINC FBINC FBINT YT(0:9) YC(0:9) FBOUTT I/O I I I I O O O Description Complementary Clock Input. Complementary Clock Input. Feedback Clock Input. Connect to FBOUTC for accessing the PLL. Feedback Clock Input. Connect to FBOUTT for accessing the PLL. Clock Outputs Clock Outputs Feedback Clock Output. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Serial Clock Input. Clocks data at SDATA into the internal register. Data Input for the two-line serial bus Data Input and Output for the two-line serial bus Differential Outputs Differential Outputs Differential Input Electrical Characteristics LV Differential Input 33 FBOUTC O 12 37 SCLK SDATA I, PU I/O, PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 2.5V power Supply for Logic 11 4, 21, 28, 34, 38, 45 16 15 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 17 VDD VDDQ AVDD VDDI VSS AVSS 2.5V Nominal 2.5V Power Supply for Output Clock Buffers 2.5V Nominal 2.5V Power Supply for PLL Power Supply for two-line serial Interface Common Ground Analog Ground 2.5V Nominal 2.5V or 3.3V Nominal 0.0V Ground 0.0V Analog Ground Notes: 1. PU= internal pull-up 2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power pin (