CY2SSTV850ZI

STV850 CY2SSTV850 Differential Clock Buffer/Driver Features Description • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:10 differential outputs • External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for EMI reduction • 48-pin SSOP and TSSOP packages • Conforms to JEDEC JC40 and JC42.5 DDR specifications This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram Pin Configuration 10 YT1 YC1 YT2 YC2 SCLK SDATA YT3 YC3 Serial Interface Logic YT4 YC4 YT5 YC5 YT6 YC6 CLKINT CLKINC YT7 YC7 PLL YT8 YC8 FBINT FBINC YT9 YC9 AVDD Cypress Semiconductor Corporation Document #: 38-07457 Rev. *A FBOUTT FBOUTC • 3901 North First Street VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKINT CLKINC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 San Jose CY2SSTV850 YT0 YC0 • 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS YC5 YT5 VDDQ YT6 YC6 VSS VSS YC7 YT7 VDDQ SDATA FBINT FBINC VDDQ FBOUTC FBOUTT VSS YC8 YT8 VDDQ YT9 YC9 VSS CA 95134 • 408-943-2600 Revised December 18, 2001 CY2SSTV850 Pin Description[1, 2] Pin 13 Name I/O CLKINT I Description Complementary Clock Input. Electrical Characteristics LV Differential Input 14 CLKINC I Complementary Clock Input. 35 FBINC I Feedback Clock Input. Connect to FBOUTC for accessing the PLL. 36 FBINT I Feedback Clock Input. Connect to FBOUTT for accessing the PLL. 3, 5, 10, 20, 22 46, 44, 39, 29,27 YT(0:9) O Clock Outputs 2, 6, 9, 19, 23 47, 43, 40,30,26 YC(0:9) O Clock Outputs 32 FBOUTT O Feedback Clock Output. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 FBOUTC O Feedback Clock Output. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 12 SCLK I, PU Serial Clock Input. Clocks data at SDATA into the internal register. 37 SDATA 11 VDD 2.5V power Supply for Logic 4, 21, 28, 34, 38, 45 VDDQ 2.5V Power Supply for Output Clock Buffers 2.5V Nominal 16 AVDD 2.5V Power Supply for PLL 2.5V Nominal 15 VDDI Power Supply for two-line serial Interface 2.5V or 3.3V Nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 VSS Common Ground 0.0V Ground 17 AVSS Analog Ground 0.0V Analog Ground I/O, PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. Differential Input Differential Outputs Differential Outputs Data Input for the two-line serial bus Data Input and Output for the two-line serial bus 2.5V Nominal Notes: 1. PU= internal pull-up 2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power pin (