CY2V995AC

CY2V995 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Features • • • • • • • • • • • • • • 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew: < 150 ps Cycle-cycle jitter: < 100 ps Selectable positive or negative edge synchronization 8 LVTTL outputs driving 50Ω terminated lines LVCMOS/LVTTL over-voltage tolerant reference input Selectable phase-locked loop (PLL) frequency range and lock indicator (1-6,8,10,12)x multiply and (1/2,1/4)x divide ratios Spread-Spectrum-compatible Power-down mode Industrial temperature range: –40°C to +85°C 44-pin TQFP package Description The CY2V995 is a low-voltage, low-power, eight output, 200-MHz clock driver. It features function necessary to optimize the timing of high-performance computer and communication systems. The user can program the frequency of the output banks through nF[0:1] and DS[0:1] pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock. Block Diagram TEST PD# PE FS VDDQ1 Pin Configuration PLL FB DS1:0 LOCK /N 3 3 4F1 1Q0 1F1:0 1Q1 sOE# PD# PE VDDQ4 VDDQ4 4Q1 4Q0 VSS VSS VSS 2Q0 2F1:0 2Q1 3F1:0 3 3 /K 3Q0 3Q1 VDDQ3 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 4F0 3F1 3F0 REF FS VDD REF VSS TEST 2F1 2F0 1F1 33 32 31 30 29 28 27 26 25 24 23 1F0 DS1 DS0 LOCK VDDQ1 VDDQ1 1Q0 1Q1 VSS VSS VSS 3 3 CY2V995 4F1:0 3 3 /M 4Q0 4Q1 VDDQ4 sOE# Cypress Semiconductor Corporation Document #: 38-07435 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2004 VSS 3Q1 3Q0 VDDQ3 VDDQ3 FB VDD VDDQ1 2Q1 2Q0 VSS CY2V995 Pin Description Pin 39 17 37 2 Name REF FB TEST sOE# I I I I, PD I/O[1] Type LVTTL/ LVCMOS LVTTL 3-Level LVTTL Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. Please see Table 8. Select frequency of the outputs. Please see Tables 3, 4, 5, and 7. Selects VCO operating frequency range. Please see Table 6. Four banks of two outputs. Please see Table 5 for frequency settings. Select feedback divider. Please see Table 1. Power-down and reference divider control. When LOW, shuts off entire chip. Please see Table 2 for settings. PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the input. Power supply for Bank 4 output buffers. Please see Table 8 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 8 for supply level constraints Power supply for Bank 1 and Bank 2 output buffers. Please see Table 8 for supply level constraints Power supply for the internal circuitry. Please see Table 8 for supply level constraints Ground Table 1. Feedback Divider Settings DS[1:0] LL LM LH ML MM MH HL HM HH N-Feedback Input Divider 2 3 4 5 1 6 8 10 12 Permitted Output Divider Connected to FB[4] 1 or 2 1 1,2 or 4 1 or 2 1,2 or 4 1 or 2 1 or 2 1 1 Description 4 PE I, PU LVTTL 34, 33, 36, 35, nF[1:0] 43, 42, 1, 44 41 26,27,20,21, 13,14,7,8 32, 31 3 30 5,6 15,16 19,28 18,40 FS nQ[1:0] DS[1:0] PD# LOCK I I O I I, PU O 3-Level 3-Level LVTTL 3-Level LVTTL LVTTL Power Power Power Power Power VDDQ4[2] PWR VDDQ3 [2] PWR VDDQ1[2] PWR VDD[2] PWR PWR 9-12, 22-25, 38 VSS Device Configuration The outputs of the CY2V995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 1. Notes: 1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (