CY2VC511ZXC

PRELIMINARY CY2VC511 27 MHz Clock Generator with VCXO Features Description ■ Generates 27 MHz Output Clock ■ Uses 27 MHz LVCMOS Reference Clock ■ LVCMOS Output The CY2VC511 is a PLL based clock generator with VCXO control. It takes a low swing 27 MHz reference clock, and generates an adjustable 27 MHz output clock. The device has a single LVCMOS output and operates from a 3.3V power supply. ■ VCXO with 230 ppm Minimum Pull Range ■ Fully Integrated Low Noise Phase Locked Loop (PLL) ■ Linear Voltage-to-Frequency Control Curve ■ Supply Voltage: 3.3V ■ Pb-free 16-Pin TSSOP Package The VIN pin is an analog input that enables the user to pull the output frequency. The pullability range is at least 230 ppm (±115 ppm). The pull curve is very linear. Unlike conventional VCXO designs, the output frequency adjustment is achieved by a proprietary PLL design. This permits the use of 27 MHz clock reference. Logic Block Diagram LOW -NOISE PLL REFIN CLK VIN Cypress Semiconductor Corporation Document Number: 001-10796 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 14, 2010 [+] Feedback PRELIMINARY CY2VC511 Pinout Figure 1. Pin Diagram - 16-Pin TSSOP REFIN 1 16 DNU VDD 2 15 VSS VDD 3 14 NC VDD 4 13 CLK NC 5 12 NC NC 6 11 DNU VSS 7 10 NC VSS 8 9 VIN Table 1. Pin Definitions - 16-Pin TSSOP Pin Name 1 REFIN 9 Type Description 1.8V CMOS Input Reference Clock Input VIN Analog Input VCXO Control Voltage - VIN has a positive control slope; that is, increasing the voltage on VIN causes the output frequency to increase The nominal output frequency is determined when VIN = 1.65V 13 CLK CMOS Output 27 MHz Output Clock 11, 16 DNU – Do Not Use: DNU pins are electrically connected, but perform no function NC – No Connect: NC pins are not connected to the die 5, 6, 10, 12, 14 2, 3, 4 VDD Power Supply Voltage: 3.3V 7, 8, 15 VSS Power Ground Document Number: 001-10796 Rev. *D Page 2 of 7 [+] Feedback PRELIMINARY CY2VC511 Frequency Table Input Reference Frequency (MHz) PLL Multiplier Value 27 1 Output Frequency (MHz) 27 VCXO and VIN Application Information The output frequency of the device is adjusted over a limited range by use of the VCXO feature. This feature is typically used to phase and frequency lock to a separate reference clock. The frequency is controlled by the analog voltage on the VIN pin. The nominal output frequency is generated when VIN = 1.65V. As the voltage on VIN is increased, the output frequency increases. The voltage range for VIN is from 0V (VSS) to VDD. The relationship between output frequency (ppm) to VIN voltage is very linear over a large portion of the control voltage range. Power Supply Filtering Techniques As in any high speed analog circuitry, noise on the power supply pins can degrade device performance. For general power plane decoupling, make certain there is at least one tantalum capacitor (~5 to 10 μF) in the general vicinity of this device. Additionally, ensure there is one or two multi-layer ceramic chip capacitors (0.01 or 0.1 μF) located as close as possible to the power and ground pins of the device. Ensure the layout is optimized to minimize power and ground inductance and locate the capacitor as close to the device pins as possible. Absolute Maximum Conditions Parameter Description Condition VDD Supply Voltage VIN[1] Input Voltage, DC TS Temperature, Storage TJ Temperature, Junction ESDHBM ESD Protection (Human Body Model) Min Max Unit –0.5 4.4 V Relative to VSS –0.5 VDD + 0.5 V Non operating –65 150 °C – 125 °C JEDEC STD 22-A114-B 2000 – V UL–94 Flammability Rating At 1/8 in ΘJA[2] Thermal Resistance, Junction to Ambient 0 m/s airflow V–0 °C/W 84 1 m/s airflow 79 2.5 m/s airflow 76 Operating Conditions Parameter Description VDD Supply Voltage Range TA Ambient Temperature TPU Power up time for VDD to reach minimum specified voltage (ensure power ramp is monotonic) CLOAD Load Capacitance on CLK output Min Typ Max Unit 3.135 3.3 3.465 V 0 – 70 °C 0.05 – 500 ms – – 15 pF Notes 1. The voltage on any input or output pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document Number: 001-10796 Rev. *D Page 3 of 7 [+] Feedback PRELIMINARY CY2VC511 DC Electrical Characteristics Parameter Description Condition IDD Operating Supply Current VDD = 3.465V, output unloaded VOH High Output Voltage VDD = min, IOH = –4 mA VOL Low Output Voltage VDD = max, IOL = 4 mA VIH Input High Voltage For REFIN VIL Input Low Voltage For REFIN VVIN VIN Input Voltage IVIN VIN Input Current INLVIN[3, 4] VIN to FOUT Integral Nonlinearity Min Typ Max Unit – – 110 mA 0.9*VDD – – V – – 0.1*VDD V 1.25 – 1.8 V – – 0.25 V 0 – VDD V VSS ≤ VIN ≤ VDD –10 – 60 μA VSS ≤ VIN ≤ VDD – 1 – % Test Conditions Min Typ Max Unit – 27 – MHz ±115 – – ppm AC Electrical Characteristics [3] Parameter Description FOUT Output Frequency PR Pull Range VIN = VDD to VSS, relative to nominal fOUT (VIN = 1.65V) across operating temperature and supply voltage. TDC Duty Cycle Measured at VDD/2, defined in Figure 2 45 50 55 % TR Output Rise Time 20% to 80% of VDD, CLOAD = 15 pF – 0.7 1.5 ns TF Output Fall Time 80% to 20% of VDD, CLOAD = 15 pF – 0.8 1.5 ns TLOCK Start Up Time Time for CLK to reach valid frequency measured from the time VDD = VDD (min) – – 5 ms Parameter Measurements Figure 2. Output Duty Cycle Timing CLK TDC = TPW TPERIOD TPW TPERIOD Figure 3. Output Rise and Fall Time 80% VDD 80% CLK 20% 20% 0V TR TF Note 3. Not 100% tested, guaranteed by design and characterization. 4. Integral nonlinearity is defined in IEEE Standard 1241-2000. Document Number: 001-10796 Rev. *D Page 4 of 7 [+] Feedback PRELIMINARY CY2VC511 Ordering Information Part Number Package Description Product Flow Pb-Free CY2VC511ZXC 16-Pin TSSOP Commercial, 0° to 70°C CY2VC511ZXCT 16-Pin TSSOP - Tape and Reel Commercial, 0° to 70°C Package Drawings and Dimensions Figure 4. 16-Pin TSSOP 4.40 mm Body 51-85091 *B Document Number: 001-10796 Rev. *D Page 5 of 7 [+] Feedback PRELIMINARY CY2VC511 Document History Page Document Title: CY2VC511 27 MHz Clock Generator with VCXO Document Number: 001-10796 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 506248 RGL See ECN New data sheet *A 1285703 JWK/KVM/ See ECN Changed definition of nominal frequency to VIN = 1.65V ARI Added CLOAD specification Changed RUP value Corrected TR/TF conditions and specification Removed pull down resistor on SEL Updated several drawings Edited data sheet for template compliance *B 2705638 XHT/KVM/ 05/13/2009 Changed title from Low Noise Clock Generator with VCXO to 27 MHz Clock AESA Generator with VCXO, Basic configuration change: Reference changed from crystal to driven clock, Output changed from 216 MHz to 27 MHz, Pinout changed to show no connects, Pin 11 changed to DNU, VDD range changed from ±0.2V to ±5%, Thermal resistance data added, IOL & IOH changed from 2mA to 4mA Phase noise specs removed, IIVIN changed from 10μA to 60μA, Rise & fall times changed, IDD changed *C 2768029 KVM 09/18/2009 Remove reference to OE/PD# pin in IDD spec Change parameter name IIVIN to IVIN Change parameter LIN to INLVIN, add note to definition Add max limit for TR, TF: 1.5 ns Change TLOCK max from 10 ms to 5 ms *D 2905106 KVM 05/14/10 Updated package diagram. Document Number: 001-10796 Rev. *D Page 6 of 7 [+] Feedback PRELIMINARY CY2VC511 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-10796 Rev. *D Revised May 14, 2010 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback