CY2VC521ZXC-2T

CY2VC521-2 Low Noise LVDS Clock Generator with VCXO Features Description ■ Output: 216 MHz Output Clock ■ Input: External 27 MHz Crystal ■ Differential LVDS Output with 2x Drive to Drive Two Loads ■ VCXO gives 230 ppm Minimum Pull Range The CY2VC521-2 is a PLL-based clock generator with VCXO control and very low output jitter. When the user connects a fundamental mode 27 MHz crystal, this device generates a 216 MHz output clock. The CY2VC521-2 has one LVDS output pair tuned to drive two standard LVDS loads and operates from a single 3.3V power supply. ■ Low RMS Phase Jitter (12 kHz–20 MHz): 1.3 ps Typical ■ Low Phase Noise ■ Fully Integrated Low Noise Phase Locked Loop (PLL) ■ Excellent Voltage-to-Frequency Linearity ■ Supply Voltage: 3.3V ■ Pb-free 16-Pin TSSOP Package The VIN pin is an analog input that enables the user to pull the output frequency. The pullability range is at least 230 ppm (±115 ppm). Unlike conventional VCXO designs, the output frequency adjustment is not achieved by adjusting capacitance at the pins of the crystal. Instead, a proprietary PLL design is used. This permits the use of a standard 27 MHz crystal. A special “pullable” crystal is neither required nore recommended. Logic Block Diagram XIN External 27 MHz Crystal CRYSTAL OSCILLATOR LOW-NOISE PLL CLK CLK# XOUT VIN SEL Cypress Semiconductor Corporation Document Number: 001-15599 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 14, 2010 [+] Feedback CY2VC521-2 Pinout Figure 1. Pin Diagram - 16-Pin TSSOP XIN 1 16 XOUT VDD 2 15 NC VDD 3 14 CLK VDD 4 13 CLK# VIN 5 12 VSS VSS 6 11 NC VSS 7 10 VDD VSS 8 9 SEL Table 1. Pin Definitions - 16-Pin TSSOP Pin Name Type Description 1 XIN Crystal Oscillator Input: Connect a 27 MHz crystal between XIN and XOUT 16 XOUT Crystal Oscillator Output: Connect a 27 MHz crystal between XIN and XOUT 5 VIN Analog Input VCXO Control Voltage: VIN has a positive control slope, meaning that increasing the voltage on VIN causes the output frequency to increase. The nominal output frequency is determined when VIN = 1.65V 13, 14 CLK#, CLK LVDS Output Differential output clock 9 SEL CMOS Input Select: Hold this pin LOW for normal operation 11, 15 NC – No Connect: NC pins are not connected to the die 2, 3, 4, 10 VDD – 3.3V power supply 6, 7, 8, 12 VSS – Ground Document Number: 001-15599 Rev. *E Page 2 of 9 [+] Feedback CY2VC521-2 Frequency Table Inputs Xtal Frequency (MHz) PLL Multiplier Value 27 8 Output Frequency (MHz) 216 VCXO and VIN Crystal Input Interface The output frequency of the device is adjusted over a limited range by use of the VCXO feature. This feature is typically used to phase and frequency lock to a separate reference clock. The frequency is controlled by the analog voltage on the VIN pin. The nominal output frequency is generated when VIN = 1.65V. As the voltage on VIN is increased, the output frequency increases. The voltage range for VIN is from 0V (VSS) to VDD. The CY2VC521-2 is designed for use with a 14 pF parallel resonant crystal. This assumes 2 pF of board capacitance on each crystal signal traces, plus 26 pF internally on both the XIN and XOUT pins. The crystal is required to meet the parameters shown in “Crystal Characteristics” on page 4. Because the frequency pulling function is implemented inside the PLL, there are no additional requirements placed on the crystal for pullability. Application Information The design may require external trimming capacitors if the crystal has CL greater than 14 pF, depending on the layout. Power Supply Filtering Techniques As in any high speed analog circuitry, noise on the power supply pins degrade device performance. For general power plane decoupling, make certain there is at least one tantalum capacitor (~5 to 10 μF) in the general vicinity of this device. Additionally, ensure one or two multi-layer ceramic chip capacitors (0.01 or 0.1 μF) is located as close as possible to the power and ground pins of the device. Make certain to optimize the layout to minimize power and ground inductance and to locate the capacitor as close to the device pins as possible. Termination for LVDS Output Use a 100Ω terminating resistor to terminate CLK and CLK# with two parallel differential traces split near the driver; connect the resistors between each pair near the receiver. This is shown in the following figure. VIN Control Figure 3 shows a typical VCXO control curve for the CY2VC521-2. The conditions are 25°C, VDD=3.3V, crystal CL=13 pF, and board capacitance on XIN and XOUT traces of 3.5 pF each. Note that the internal capacitance measured on the XIN and XOUT pins is approximately 26 pF. In this case the curve is not centered (0 ppm at VIN=VDD/2) because the capacitive loading on the crystal is too high, which causes it to oscillate slower than its nominal frequency. When the crystal is capacitively loaded as specified (CL), it oscillates at its specified frequency, and the VCXO control curve is nominally centered. Such changes in the crystal oscillation frequency result in a vertical shift of the curve. The slope and linearity of the curve are independent of the crystal characteristics. Figure 3. Typical VCXO Control Curve Figure 2. LVDS Output Termination 150 Z0 = 50Ω 100 100Ω PPM from 216MHz CLK CLK# Z0 = 50Ω 100Ω Z0 = 50Ω 50 IN Z0 = 50Ω IN 0 -50 -100 -150 -200 -250 0 0.5 1 1.5 2 2.5 3 3.5 VIN Voltage Document Number: 001-15599 Rev. *E Page 3 of 9 [+] Feedback CY2VC521-2 Absolute Maximum Conditions Parameter Description Min Max Unit –0.5 4.4 V Relative to VSS –0.5 VDD+0.5 V Non Operating –65 150 °C – 135 °C ESD Protection (Human Body Model) JEDEC STD 22-A114-B 2000 – V UL–94 Flammability Rating At 1/8 in. ΘJA[5] Thermal Resistance, Junction to Ambient 0 m/s airflow VDD Supply Voltage VIN[1] Input Voltage, DC TS Temperature, Storage TJ Temperature, Junction ESDHBM Condition V–0 °C/W 84 1 m/s airflow 79 2.5 m/s airflow 76 Operating Conditions Min Typ Max Unit VDD Parameter Supply Voltage Range Description 3.15 3.3 3.45 V TPU Power up time for VDD to reach VDD(min). (Ensure power ramp is monotonic.) 0.05 – 500 ms TA Ambient Temperature 0 – 70 °C Typ Max Unit Crystal Characteristics Parameter Description Min Mode of Oscillation Fundamental F Frequency – 27 – MHz CL Load Capacitance – 14 – pF ESR Equivalent Series Resistance – – 50 Ω CS Shunt Capacitance – – 7 pF Min Typ Max Unit – – 120 mA DC Electrical Characteristics Parameter Description Condition IDD[3] Power Supply Current VOD LVDS Differential Output Voltage 247 350 454 mV ΔVOD LVDS VOD Magnitude Change –50 – 50 mV VOS LVDS Offset Output Voltage 1.125 1.25 1.375 mV ΔVOS LVDS VOS Magnitude Change –25 – 25 mV Outputs on and terminated VIH Input High Voltage, SEL 0.7*VDD – – V VIL Input Low Voltage, SEL – – 0.3*VDD V IIH Input High Current, SEL SEL = VDD – – 10 μA IIL Input Low Current, SEL SEL = VSS – – 20 μA CIN [5] Input Capacitance, SEL – 4 – pF VVIN VIN Input Voltage 0 – VDD V IVIN VIN Input Current VSS ≤ VIN ≤ VDD –10 – 60 μA INLVIN[4, 5] VIN to FOUT Integral Nonlinearity VSS ≤ VIN ≤ VDD – 1 – % Notes 1. The voltage on any input or output pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model 3. IDD includes ~8 mA of current that is dissipated externally in the output termination resistors. 4. Not 100% tested, guaranteed by design and characterization. 5. Integral nonlinearity is defined in IEEE Standard 1241-2000. Document Number: 001-15599 Rev. *E Page 4 of 9 [+] Feedback CY2VC521-2 AC Electrical Characteristics[4, 6] Parameter Description FOUT Output Frequency PR Pull Range TR, TF[7] Output Rise and Fall Times TJ Period Jitter, RMS Test Conditions Min Typ Max Unit – 216 – MHz VIN = VDD to VSS, relative to frequency at VIN = 1.65V, across operating temperature and voltage range ±115 – – ppm 20% and 80% of swing between steady state levels – – 0.5 ns – 7 – ps TJitter(φ) RMS Phase Jitter (Random) 216 MHz carrier, integrated 12 kHz–20 MHz – 1.3 – ps PN Phase Noise 1 kHz offset from 216 MHz carrier – –95 – dBc/Hz 10 kHz offset from 216 MHz carrier – –120 – dBc/Hz 100 kHz offset from 216 MHz carrier – –127 – dBc/Hz 1 MHz offset from 216 MHz carrier – –123 – dBc/Hz 10 MHz offset from 216 MHz carrier – –130 – dBc/Hz TDC[8] Duty Cycle Measured at zero crossing point 45 50 55 % TLOCK Start-up Time Time for CLK to reach valid frequency measured from the time VDD = VDD (min.) – – 5 ms Notes 6. Outputs are terminated with 50Ω between CLK and CLK#. Refer to Figure 2 on page 3. 7. Refer to Figure 6 on page 6. 8. Refer to Figure 7 on page 6. Document Number: 001-15599 Rev. *E Page 5 of 9 [+] Feedback CY2VC521-2 Parameter Measurements Figure 4. Output Voltage Swing CLK# V OD1 V OD2 CLK ΔV OD = V OD1 - V OD2 Figure 5. Output Offset Voltage CLK 25Ω VOS 25Ω CLK# Figure 6. Output Rise and Fall Time CLK# CLK 80% 80% 20% 20% TF TR Figure 7. Output Duty Cycle/Pulse Width/Period CLK TDC = TPW TPERIOD CLK# TPW TPERIOD Document Number: 001-15599 Rev. *E Page 6 of 9 [+] Feedback CY2VC521-2 Ordering Information Part Number Package Description Product Flow Pb-Free CY2VC521ZXC-2 16-Pin TSSOP Commercial, 0° to 70°C CY2VC521ZXC-2T 16-Pin TSSOP - Tape and Reel Commercial, 0° to 70°C Package Drawings and Dimensions Figure 8. 16-Pin TSSOP 4.40 MM Body 51-85091 *B Document Number: 001-15599 Rev. *E Page 7 of 9 [+] Feedback CY2VC521-2 Document History Page Document Title: CY2VC521-2 Low Noise LVDS Clock Generator with VCXO Document Number: 001-15599 REV. ECN NO. Submission Date Orig. of Change ** 1285703 See ECN JWK/ARI *A 2669117 3/5/2009 *B 2697706 04/20/2009 KVM/PYRS Added VCXO Control Curve figure and text *C 2705609 05/15/2009 KVM/AESA Corrected part numbers in Ordering Information table Added phase jitter spec to AC Electrical table, and added conditions to the phase jitter claim in the features section of page 1 Formatting improvements Corrected conditions for ESD *D 2768029 09/18/2009 KVM Change parameter name IIVIN to IVIN Change parameter LIN to INLVIN, add note to definition INLVIN & CIN reference note: not 100% tested Change TLOCK max from 10 ms to 5 ms Change part number CY2VC521ZXCT-2 to CY2VC521ZXC-2T *E 2905106 05/14/10 KVM Updated package diagram. Document Number: 001-15599 Rev. *E Description of Change New datasheet Created from 001-06436 Edited data sheet for template compliance KVM/AESA Removed MSL spec IIL changed from 100 μA to 20 μA Changed phase noise values Replaced jitter with phase jitter in Features list Changes to VOD specs Change IIVIN max from 50uA to 60uA; added min value Changed junction temp from 125°C to 135°C Changed Data Sheet Status to Final Page 8 of 9 [+] Feedback CY2VC521-2 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-15599 Rev. *E Revised May 14, 2010 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback