CY2XF33
High-Performance LVDS Oscillator With Frequency Margining – Pin Control
Features
■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Functional Description
The CY2XF33 is a high-performance and high-frequency crystal oscillator (XO). It uses a Cypress proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications. The CY2XF33 is available as a factory configured device or as a field programmable device.
Low jitter crystal oscillator (XO) Less than 1 ps typical RMS phase jitter Differential LVDS output Output frequency from 50 MHz to 690 MHz Two frequency margining control pins (FS0, FS1) Factory configured or field programmable Integrated phase-locked loop (PLL) Supply voltage: 3.3 V or 2.5 V Pb-free package: 5.0 × 3.2 mm LCC Commercial and industrial temperature ranges
Logic Block Diagram
4 Crystal Oscillator Low-Noise PLL Output Divider 5 FS1 1
Frequency Select Decode
CLK
CLK#
FS0
2
Pinouts
Figure 1. Pin Diagram – 6-Pin Ceramic LCC
FS1 1 FS0 2 VSS 3
6 VDD 5 CLK# 4 CLK
Table 1. Pin Definitions – 6-Pin Ceramic LCC Pin 1, 2 4, 5 6 3 Name FS1, FS0 CLK, CLK# VDD VSS I/O Type CMOS input LVDS output Power Power Frequency select Differential output clock Supply voltage: 2.5 V or 3.3 V Ground Description
Cypress Semiconductor Corporation Document Number: 001-53148 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised June 13, 2011
CY2XF33
Contents
Pinouts .............................................................................. 1 Contents ............................................................................ 2 Functional Description ..................................................... 3 Programming Description ............................................... 3 Field Programmable CY2XF33F ................................. 3 Factory Configured CY2XF33 ..................................... 3 Application-Specific Factory Configurations ................ 4 Programming Variables ................................................... 4 Output Frequencies ..................................................... 4 Industrial Versus Commercial Device Performance .... 4 Phase Noise Versus Jitter Performance ..................... 4 Absolute Maximum Conditions ....................................... 5 Operating Conditions ....................................................... 5 DC Electrical Characteristics .......................................... 5 AC Electrical Characteristics ........................................... 6 Termination Circuits ......................................................... 6 Switching Waveforms ...................................................... 7 Ordering Information ........................................................ 8 Possible Configuration ................................................ 8 Ordering Code Definitions ........................................... 8 Package Drawings and Dimensions ............................... 9 .Acronyms ....................................................................... 10 Document Conventions ................................................. 10 Units of Measures ..................................................... 10 Document History Page ................................................. 11 Sales, Solutions, and Legal Information ...................... 11 Worldwide Sales and Design Support ....................... 11 Products .................................................................... 11 PSoC Solutions ......................................................... 11
Document Number: 001-53148 Rev. *E
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CY2XF33
Functional Description
The FS0 and FS1 pins select between four different output frequencies, as shown in Table 3. Frequency margining is a common application for this feature. One frequency is used for the standard operating mode of the device, while the other frequencies are available for margin testing, either during product development or in system manufacturing test. Table 2. Frequency Select FS1 0 0 1 1 FS0 0 1 0 1 Output Frequency Frequency 0 Frequency 1 Frequency 2 Frequency 3
Field Programmable CY2XF33F
Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocks™ Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress’s value added distribution partners also provide programming services. Field programmable devices are designated with an “F” in the part number. They are intended for quick prototyping and inventory reduction. The CY2XF33 is one time programmable (OTP). The software is located at CyberClocks(TM) Online Software.
Factory Configured CY2XF33
For customers wanting ready-to-use devices, the CY2XF33 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders.
When changing the output frequency, the frequency transition is not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency. Glitches and runt pulses are possible, and time must be allowed for the PLL to relock.
Programming Description
The CY2XF33 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections.5
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CY2XF33
Application-Specific Factory Configurations
Part Number CY2XF33LXC700T VDD 3.3 V FS1 0 0 1 1 FS0 0 1 0 1 Output Frequency 100.00 MHz 125.00 MHz 200.00 MHz 250.00 MHz Table 3. Device Programming Variables Variable Output frequency 0 (Power on default) Output frequency 1 Output frequency 2 Output frequency 3 Optimization (phase noise or jitter) Temperature range (Commercial or industrial) RMS Phase Jitter (Random) Offset Range 12 kHz to 20 MHz Jitter (Typical) 0.65 ps 0.61 ps 0.55 ps 0.53 ps
Programming Variables
Output Frequencies
The CY2XF33 is programmed with up to four independent output frequencies, which are then selected using the FS0 and FS1 pins. The device can synthesize frequencies to a resolution of 1 part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2XF33 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2XF33 cannot generate frequencies in the ranges of 521 MHz to 529 MHz and 596 MHz to 617 MHz.
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal crystals. This has a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options.
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter.
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CY2XF33
Absolute Maximum Conditions
Parameter VDD VIN[1] TS TJ ESDHBM JA[2] Description Supply voltage Input voltage, DC Temperature, storage Temperature, junction ESD protection (human body model) – Relative to VSS Non operating – JEDEC STD 22-A114-B Condition Min –0.5 –0.5 –55 –40 2000 64 Max 4.4 VDD + 0.5 135 135 – Unit V V C C V C/W
Thermal resistance, junction to ambient 0 m/s airflow
Operating Conditions
Parameter VDD TPU TA 3.3 V supply voltage range 2.5 V supply voltage range Power up time for VDD to reach minimum specified voltage (power ramp is monotonic) Ambient temperature (commercial) Ambient temperature (industrial) Description Min 3.135 2.375 0.05 0 –40 Typ 3.3 2.5 – – – Max 3.465 2.625 500 70 85 Unit V V ms C C
DC Electrical Characteristics
Parameter IDD[3] Description Operating supply current Condition VDD = 3.465 V, CLK = 150 MHz, output terminated VDD = 2.625 V, CLK = 150 MHz, output terminated VOD VOD VOS VOS VIH VIL IIH0 IIH1 IIL0 IIL1 CIN0[4] CIN1[4] LVDS differential output voltage Change in VOD between complementary output states LVDS offset output voltage Change in VOS between complementary output states Input high voltage Input low voltage Input high current, FS0 pin Input high current, FS1 pin Input low current, FS0 pin Input low current, FS1 pin Input capacitance, FS0 pin Input capacitance, FS1 pin VDD = 3.3 V or 2.5 V, defined in Figure 3 as terminated in Figure 2 VDD = 3.3 V or 2.5 V, defined in Figure 3 as terminated in Figure 2 VDD = 3.3 V or 2.5 V, defined in Figure 4 as terminated in Figure 2 VDD = 3.3 V or 2.5 V, RTERM = 100 between CLK and CLK# – – Input = VDD Input = VDD Input = VSS Input = VSS – – Min – – 247 – 1.125 – 0.7 × VDD – – – –50 –20 – – Typ – – – – – – – – – – – – 15 4 Max 120 115 454 50 1.375 50 – 0.3 × VDD 115 10 – – – – Unit mA mA mV mV V mV V V A A A A pF pF
Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. 4. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53148 Rev. *E
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CY2XF33
AC Electrical Characteristics[5]
Parameter FOUT FSC FSI AG TDC Description Output frequency[6] Frequency stability, commercial devices[7] Aging, 10 years Output duty cycle – TA = 0 °C to 70 °C Condition Min 50 – – – 45 40 – – – – Typ – – – – 50 50 0.35 – – 1 Max 690 ±35 ±55 ±15 55 60 1.0 5 1 – Unit MHz ppm ppm ppm % % ns ms ms ps
Frequency stability, industrial devices[7] TA = –40 °C to 85 °C – F 450 MHz, measured at zero crossing F > 450 MHz, measured at zero crossing
TR, TF TLOCK TLFS TJitter()
Output rise and fall time Startup time Re-lock time RMS phase jitter (random)
20% and 80% of full output swing Time for CLK to reach valid frequency measured from the time VDD = VDD(min) Time for CLK to reach valid frequency from FS0 or FS1 pin change fOUT = 106.25 MHz (12 kHz–20 MHz)
Termination Circuits
Figure 2. LVDS Termination
CLK 100 CLK#
Notes 5. Not 100% tested, guaranteed by design and characterization. 6. This parameter is specified in CyberClocks Online software. 7. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
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CY2XF33
Switching Waveforms
Figure 3. Output Voltage Swing
CLK# VOD1 CLK VOD = VOD1 - VOD2
Figure 4. Output Offset Voltage
VOD2
CLK
50 50
CLK#
V OS
Figure 5. Output Duty Cycle Timing
CLK TDC = CLK# TPW TPERIOD TPW TPERIOD
Figure 6. Output Rise and Fall Time
CLK#
20% TR
80%
80% 20% TF
CLK
Figure 7. RMS Phase Jitter
Phase noise
Noise Power Phase noise mark
Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot
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CY2XF33
Ordering Information
Part Number Pb-free CY2XF33FLXCT CY2XF33FLXIT CY2XF33LXC700T[8] Field programmable Field programmable Factory-configured 6-pin ceramic LCC SMD – Tape and Reel 6-pin ceramic LCC SMD – Tape and Reel 6-pin ceramic LCC SMD – tape and reel Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Configuration Package Description Product Flow
Possible Configuration
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for more information. Part Number[9] Pb-free CY2XF33LXCxxxT CY2XF33LXIxxxT Factory configured Factory configured 6-pin ceramic LCC SMD – Tape and Reel 6-Pin ceramic LCC SMD – Tape and Reel Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Configuration Package Description Product Flow
Ordering Code Definitions
CY xx xxx L X X xxx T
T = Tape and Reel Customer Specific Code Temperature Range: C = Commercial, I = Industrial Pb-free Package type Part identifier Family Company ID: CY = Cypress
Notes 8. Device configuration details are described in the “Application-Specific Factory Configurations” on page 4. 9. “xxx” is a factory assigned code that identifies the programming option.For more details, contact your local Cypress FAE or Sales Representative.
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CY2XF33
Package Drawings and Dimensions
Figure 8. 6-Pin 3.2 × 5.0 mm Ceramic LCC LZ06A
0.50
SIDE VIEW
1.30 Max
2.54 TYP. 0.64 TYP.
0.10 R REF. TYP. TYP. 0.20 R REF.
4 5 6
5.0
0.32 R INDEX
7
10
TYP.
9 8 3 2 1
TOP VIEW BOTTOM VIEW
Dimensions in mm General Tolerance: ± 0.15MM Kyocera dwg ref KD-VA6432-A Package Weight ~ 0.12 grams
001-10044-*A
.
Document Number: 001-53148 Rev. *E
0.10 REF.
Page 9 of 12
0.45 REF.
1.27
3.2
1.2 TYP.
CY2XF33
Acronyms
Acronym CLKOUT CMOS DPM EPROM LVDS NTSC OE PAL PD PLL PPM TTL clock output complementary metal oxide semiconductor die pick map erasable programmable read only memory low-voltage differential signaling national television system committee output enable phase alternate line power-down phase-locked loop parts per million transistor-transistor logic °C kHz k MHz M µA µs µV µVrms mA mm ms mV nA ns nV Description
Document Conventions
Units of Measure
Symbol kilohertz kilohm megahertz megaohm microampere microsecond microvolt microvolts root-mean-square milliampere millimeter millisecond millivolt nanoampere nanosecond nanovolt ohm Unit of Measure degrees Celsius
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CY2XF33
Document History Page
Document Title: CY2XF33 High-Performance LVDS Oscillator With Frequency Margining – Pin Control Document Number: 001-53148 Revision ** *A *B ECN 2704379 2734005 2764787 Orig. of Change WWZ KVM Submission Date 07/09/2009 Post to external web 09/18/2009 Change VOD limits from 250/450 mV to 247/454 mV Add max limit for TR, TF: 1.0 ns Change TLOCK max from 10 ms to 5 ms Change TLFS max from 10 ms to 1 ms 03/24/2010 Moved ‘xxx’ parts to Possible Configurations table. Updated package diagram. 02/10/2011 Removed “Preliminary” tag from the document. Added “Application Specific Factory Configurations” section. Added application specific part numbers and note in Ordering Code Information. 06/13/2011 Swapped FS0 and FS1 in Logic Block Diagram, Pinouts and Pin Definition on page 1. Removed CY2XF33LXC533T from “Application Specific Factory Configurations” and “Ordering Information table.” Description of Change
KVM/PYRS 05/11/2009 New data sheet
*C *D
2898472 3165931
KVM BASH
*E
3279652
BASH
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CY2XF33
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53148 Rev. *E
Revised June 13, 2011
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