CY2XP21ZXI

PRELIMINARY CY2XP21 125 MHz LVPECL Clock Generator Features ■ ■ ■ ■ ■ ■ ■ Functional Description The CY2XP21 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate a 125 MHz clock, which is ideal for 10 Gb Ethernet applications. It also produces an output frequency that is five times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP21 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL Output Pair Output Frequency: 112 MHz to 140 MHz External Crystal Frequency: 22.4 MHz to 28 MHz Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal (1.875 MHz to 20 MHz): 0.4 ps (Typical) Pb-free 8-Pin TSSOP Package Supply Voltage: 3.3V or 2.5V Commercial and Industrial Temperature Ranges Logic Block Diagram XIN External Crystal XOUT CRYSTAL OSCILLATOR LOW -N OISE PLL O UTPUT DIVIDER CLK CLK# Pinouts Figure 1. Pin Diagram - 8-Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# NC Table 1. Pin Definition - 8-Pin TSSOP Pin Number 1, 8 2 3, 4 5 6,7 Pin Name VDD VSS XOUT, XIN NC CLK#, CLK LVPECL output Power Power XTAL output and input I/O Type 3.3V or 2.5V power supply Ground Parallel resonant crystal interface No Connect Differential Clock Output Description Cypress Semiconductor Corporation Document #: 001-52849 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2009 [+] [+] Feedback PRELIMINARY CY2XP21 Frequency Table Inputs Crystal Frequency (MHz) 25 26.6 PLL Multiplier Value 5 5 Output Frequency (MHz) 125 133 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM UL–94 ΘJA[2] Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection, Human Body Model Flammability Rating Thermal Resistance, Junction to Ambient JEDEC STD 22-A114-B At 1/8 in. 0 m/s airflow 1 m/s airflow 2.5 m/s airflow 2000 V–0 100 91 87 °C/W Relative to VSS Non operating Description Conditions Min –0.5 –0.5 –65 Max 4.4 VDD + 0.5 150 135 Unit V V °C °C V Operating Conditions Parameter VDD TA TPU 3.3V Supply Voltage 2.5V Supply Voltage Ambient Temperature, Commercial Ambient Temperature, Industrial Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) Description Min 3.135 2.375 0 –40 0.05 Max 3.465 2.625 70 85 500 Unit V V °C °C ms DC Electrical Characteristics Parameter IDD[4] VOH VOL VOD1 VOD2 VOCM CINX Description Operating Supply Current with output terminated LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Peak-to-Peak Output Voltage Swing LVPECL Output Voltage Swing (VOH - VOL) Test Conditions VDD = 3.465V, Output terminated VDD = 2.625V, Output terminated Min – – Typ – – – – – – – 4.5 Max 150 145 VDD –0.75 VDD –1.625 1000 1000 – Unit mA mA V V mV mV V pF VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –1.15 VDD – 2.0V VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V VDD –2.0 600 500 1.2 LVPECL Output Common Mode VDD = 2.5V, RTERM = 50Ω to VDD – Voltage (VOH + VOL)/2 1.5V Pin Capacitance, XIN & XOUT Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes approximately 24 mA of current that is dissipated externally in the output termination resistors. Document #: 001-52849 Rev. *A Page 2 of 7 [+] [+] Feedback PRELIMINARY CY2XP21 AC Electrical Characteristics[4] Parameter FOUT TR, TF TJitter(φ) TDC TLOCK Description Output Frequency Output Rise or Fall Time RMS Phase Jitter (Random) Output Duty Cycle Startup Time 20% to 80% of full output swing 125 MHz, (1.875–20 MHz) Measured at zero crossing point Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) Conditions Min 112 – – 48 – Typ – 500 0.4 – – Max 140 – – 52 10 Unit MHz ps ps % ms Recommended Crystal Specifications[5] Parameter Mode F ESR C0 Mode of Oscillation Frequency Equivalent Series Resistance Shunt Capacitance Description Min 22.4 – – Max 28 50 7 Unit MHz Ω pF Fundamental Parameter Measurements Figure 2. 3.3V Output Load AC Test Circuit 2V Z = 50Ω SCOPE CLK 50Ω Z = 50Ω CLK# 50Ω -1.3V +/- 0.165V VDD LVPECL VSS Figure 3. 2.5V Output Load AC Test Circuit 2V Z = 50Ω SCOPE CLK 50Ω Z = 50Ω CLK# 50Ω -0.5V +/- 0.125V VDD LVPECL VSS Notes 4. INot 100% tested, guaranteed by design and characterization. 5. Characterized using an 18 pF parallel resonant crystal. Document #: 001-52849 Rev. *A Page 3 of 7 [+] [+] Feedback PRELIMINARY CY2XP21 Figure 4. Output DC Parameters CLK VOD CLK# VA VOCM = (V A + VB)/2 VB Figure 5. Output Rise and Fall Time CLK# 20% TR 80% 80% 20% TF CLK Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mask Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Document #: 001-52849 Rev. *A Page 4 of 7 [+] [+] Feedback PRELIMINARY CY2XP21 Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 8 illustrates a typical filtering scheme. Since all the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. Figure 8. Power Supply Filtering Figure 9. LVPECL Output Termination 3.3V 125Ω Z0 = 50Ω 125Ω CLK Z0 = 50Ω 84Ω 84Ω IN CLK# Crystal Interface V DD (Pin 8) 3.3V 0.1μF 0.01 µF 10µF The CY2XP21 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 10 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are thus layout dependent. Figure 10. Crystal Input Interface XIN VDD (Pin 1) Termination for LVPECL Output The CY2XP21 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3V operation, this data sheet specifies output levels for termination to VDD–2.0V. This same termination voltage can also be used for VDD = 2.5V operation, or it can be terminated to VDD-1.5V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 9 shows a standard termination scheme. X1 18 pF Parallel Crystal C1 30 pF Device XOUT C2 27 pF Board Layout and NC Pin Pin 5 (NC) does not perform any function on the CY2XP21. Although not used electrically, it is very useful for heat dissipation. For this reason, users are advised to connect pin 5 to either a VDD or VSS plane. This helps to lower the thermal resistance of the board / package combination, thus reducing the die temperature. Document #: 001-52849 Rev. *A Page 5 of 7 [+] [+] Feedback PRELIMINARY CY2XP21 Ordering Information Part Number CY2XP21ZXC CY2XP21ZXCT CY2XP21ZXI CY2XP21ZXIT Package Type 8-pin TSSOP 8-pin TSSOP - Tape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to 85°C Industrial, -40°C to 85°C Package Drawing and Dimensions Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.19[0.007] 0.30[0.012] 0.65[0.025] BSC. 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document #: 001-52849 Rev. *A Page 6 of 7 [+] [+] Feedback PRELIMINARY CY2XP21 Document History Page Document Title: CY2XP21 125 MHz LVPECL Clock Generator Document Number: 001-52849 REV. ** *A ECN NO. 2700242 2718898 Submission Date 04/30/2009 06/15/09 Orig. of Change KVM/PYRS New data sheet WWZ Minor ECN to post data sheet to external web Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-52849 Rev. *A Revised June 15, 2009 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] [+] Feedback