CY2XP22ZXIT

CY2XP22 Crystal to LVPECL Clock Generator Crystal to LVPECL Clock Generator Features Functional Description ■ One LVPECL output pair ■ Selectable frequency multiplication: × 2.5 or × 5 ■ External crystal frequency: 25.0 MHz ■ Output frequency: 62.5 MHz or 125 MHz ■ Low RMS phase jitter at 125 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.4 ps (typical) ■ Phase noise at 125 MHz (typical): Offset Noise Power 1 kHz –117 dBc/Hz 10 kHz –126 dBc/Hz 100 kHz –131 dBc/Hz 1 MHz –131 dBc/Hz The CY2XP22 is a PLL (Phase Locked Loop) based high performance clock generator that uses an external reference crystal. It is specifically targeted at FibreChannel and Gigabit Ethernet applications. It produces a selectable output frequency that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal, the user can select either a 62.5 MHz or 125 MHz output. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP22 has a crystal oscillator interface input and one LVPECL output pair. For a complete list of related documentation, click here. ■ Pb-free 8-pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial and Industrial temperature range Logic Block Diagram XIN External Crystal CRYSTAL OSCILLATOR LOW -NOISE PLL OUTPUT DIVIDER CLK CLK# XOUT F _SEL Cypress Semiconductor Corporation Document Number: 001-10229 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 12, 2018 CY2XP22 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Frequency Table ............................................................... 3 Application Information ................................................... 4 Power Supply Filtering Techniques ............................. 4 Termination for LVPECL Output .................................. 4 Crystal Interface .......................................................... 4 Absolute Maximum Conditions ....................................... 5 Operating Conditions ....................................................... 5 DC Electrical Characteristics .......................................... 6 AC Electrical Characteristics .......................................... 7 Recommended Crystal Specifications ........................... 7 Parameter Measurements ................................................ 8 Document Number: 001-10229 Rev. *I Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY2XP22 Pinouts Figure 1. 8-pin TSSOP pinout VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# F_SEL Pin Definitions 8-pin TSSOP Pin Number Pin Name I/O Type Description 1, 8 VDD Power 3.3 V or 2.5 V power supply 2 VSS Power Ground 3, 4 XOUT, XIN 5 F_SEL CMOS input 6, 7 CLK#, CLK LVPECL output XTAL output and input Parallel resonant crystal interface Frequency Select: see Frequency Table Differential clock output Frequency Table Inputs PLL Multiplier Value Output Frequency (MHz) 0 5 125 1 2.5 62.5 Crystal Frequency (MHz) F_SEL 25 Document Number: 001-10229 Rev. *I Page 3 of 15 CY2XP22 Application Information Figure 3. LVPECL Output Termination 3.3V Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 2 illustrates a typical filtering scheme. Since all the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. Figure 2. Power Supply Filtering 3.3V F 0.01 µF 125 CLK CLK# IN Z0 = 50 84 84 Crystal Interface V DD (Pin 8) VDD (Pin 1) 125 Z0 = 50 10µF The CY2XP22 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 4 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are thus layout dependent. Figure 4. Crystal Input Interface XIN Termination for LVPECL Output The CY2XP22 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3 V operation, this data sheet specifies output levels for termination to VDD – 2.0 V. This same termination voltage can also be used for VDD = 2.5 V operation, or it can be terminated to VDD – 1.5 V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 3 shows a standard termination scheme. Document Number: 001-10229 Rev. *I X1 18 pF Parallel Crystal C1 30 pF Device XOUT C2 27 pF Page 4 of 15 CY2XP22 Absolute Maximum Conditions Parameter Description Min Max Unit –0.5 4.4 V Relative to VSS –0.5 VDD + 0.5 V Non operating –65 150 C – 135 C ESD Protection, Human Body Model JEDEC STD 22-A114-B 2000 – V UL–94 Flammability Rating At 1/8 in. JA[2] Thermal Resistance, Junction to 0 m/s airflow Ambient 1 m/s airflow VDD Supply Voltage VIN[1] Input Voltage, DC TS Temperature, Storage TJ Temperature, Junction ESDHBM Conditions V–0 C/W 100 91 2.5 m/s airflow 87 Operating Conditions Parameter VDD TA TPU Description Min Max Unit 3.3 V Supply Voltage 3.135 3.465 V 2.5 V Supply Voltage 2.375 2.625 V 0 70 C Ambient Temperature, Industrial –40 85 C Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms Ambient Temperature, Commercial Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document Number: 001-10229 Rev. *I Page 5 of 15 CY2XP22 DC Electrical Characteristics Parameter IDD IDDT Description Operating Supply Current with output unterminated Operating Supply Current with output terminated Test Conditions Min Typ Max Unit VDD = 3.465 V, FOUT = 125 MHz, output unterminated – – 125 mA VDD = 2.625 V, FOUT = 125 MHz, output unterminated – – 120 mA VDD = 3.465 V, FOUT = 125 MHz, output terminated – – 150 mA VDD = 2.625 V, FOUT = 125 MHz, output terminated – – 145 mA VOH LVPECL Output High Voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD – 1.15 – VDD – 0.75 V VOL LVPECL Output Low Voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD – 2.0 – VDD – 1.625 V VOD1 LVPECL Peak-to-Peak Output Voltage Swing VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V 600 – 1000 mV VOD2 LVPECL Output Voltage Swing (VOH – VOL) VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V 500 – 1000 mV VOCM 1.2 – – V VIH LVPECL Output Common Mode VDD = 2.5 V, Voltage (VOH + VOL)/2 RTERM = 50  to VDD – 1.5 V Input High Voltage, F_SEL 0.7 × VDD – VDD + 0.3 V VIL Input Low Voltage, F_SEL –0.3 – 0.3 × VDD V IIH Input High Current, F_SEL F_SEL = VDD – – 115 µA IIL Input Low Current, F_SEL F_SEL = VSS –50 – – µA CIN[3] Input Capacitance, F_SEL – 15 – pF CINX[3] Pin Capacitance, XIN & XOUT – 4.5 – pF Note 3. Not 100% tested, guaranteed by design and characterization. Document Number: 001-10229 Rev. *I Page 6 of 15 CY2XP22 AC Electrical Characteristics Parameter [4] Description Min Typ Max Unit 62.5 – 125 MHz 20% to 80% of full output swing – 0.5 1.0 ns RMS Phase Jitter (Random) 125 MHz, (1.875–20 MHz) – 0.4 – ps TDC Output Duty Cycle Measured at zero crossing point 48 50 52 % TLOCK Startup Time Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) – – 5 ms TLFS Re-lock Time Time for CLK to reach valid frequency from F_SEL pin change – – 1 ms Min Max Unit FOUT Output Frequency TR, TF Output Rise or Fall Time TJitter() Conditions Recommended Crystal Specifications Parameter [5] Mode Description Mode of Oscillation Fundamental F Frequency 25 25 MHz ESR Equivalent Series Resistance – 50  C0 Shunt Capacitance – 7 pF Notes 4. Not 100% tested, guaranteed by design and characterization. 5. Characterized using an 18 pF parallel resonant crystal. Document Number: 001-10229 Rev. *I Page 7 of 15 CY2XP22 Parameter Measurements Figure 5. 3.3 V Output Load AC Test Circuit 2V Z = 50 VDD SCOPE CLK 50 LVPECL Z = 50 VSS CLK# 50 -1.3V +/- 0.165V Figure 6. 2.5 V Output Load AC Test Circuit 2V VDD SCOPE Z = 50 CLK Z = 50 CLK# 50 LVPECL VSS 50 -0.5V +/- 0.125V Figure 7. Output DC Parameters VA CLK VOD VOCM = (V A + VB)/2 CLK# VB Figure 8. Output Rise and Fall Time CLK# CLK 80% 20% 20% TR Document Number: 001-10229 Rev. *I 80% TF Page 8 of 15 CY2XP22 Parameter Measurements (continued) Figure 9. RMS Phase Jitter Phase noise Noise Power Phase noise mask Offset Frequency f2 f1 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 10. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Document Number: 001-10229 Rev. *I Page 9 of 15 CY2XP22 Ordering Information Part Number Package Type Product Flow CY2XP22ZXI 8-pin TSSOP Industrial, –40 C to 85 C CY2XP22ZXIT 8-pin TSSOP – Tape and Reel Industrial, –40 C to 85 C Ordering Code Definitions CY 2X P22 Z X I X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: Z = 8-pin TSSOP Part Identifier Family Company ID: CY = Cypress Document Number: 001-10229 Rev. *I Page 10 of 15 CY2XP22 Package Diagram Figure 11. 8-pin TSSOP (4.40 mm Body) Package Outline, 51-85093 51-85093 *E Document Number: 001-10229 Rev. *I Page 11 of 15 CY2XP22 Acronyms Acronym Document Conventions Description Units of Measure CLKOUT Clock Output CMOS Complementary Metal Oxide Semiconductor °C degree Celsius DPM Die Pick Map kHz kilohertz EPROM Erasable Programmable Read Only Memory k kilohm LVDS Low-Voltage Differential Signaling MHz megahertz LVPECL Low-Voltage Positive Emitter Coupled Logic M megaohm NTSC National Television System Committee µA microampere OE Output Enable PAL Phase Alternate Line PD Power-Down PLL Phase Locked Loop TTL Transistor-Transistor Logic Document Number: 001-10229 Rev. *I Symbol Unit of Measure µs microsecond µV microvolt µVrms microvolts root-mean-square mA milliampere mm millimeter ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt  ohm ppm parts per million V volt Page 12 of 15 CY2XP22 Document History Page Document Title: CY2XP22, Crystal to LVPECL Clock Generator Document Number: 001-10229 Revision ECN Orig. of Change Submission Date ** 506262 RGL 09/27/2006 Description of Change New data sheet *A 838060 RGL 03/12/2007 Changed status from Advance to Preliminary *B 2700242 KVM / PYRS 04/30/2009 Updated Features: Updated details under “Phase Noise at 125 MHz”. Updated Pinouts: Replaced VCCA with VDD. Replaced VEE with VSS. Replaced VCC with VDD. Updated Pin Definitions: Replaced VCCA with VDD. Replaced VCC with VDD. Replaced VEE with VSS. Updated details in “I/O Type” and “Description” columns for all pins. Updated Frequency Table: Added a column “PLL Multiplier Value” and added details in that column. Updated Application Information: Updated Power Supply Filtering Techniques: Updated Figure 2. Updated description. Removed “Termination for 3.3V LVPECL Output”. Added “Termination for LVPECL Output”. Updated Crystal Interface: Updated description. Updated Absolute Maximum Conditions: Replaced VCC with VDD. Changed maximum value of TJ parameter from 125 °C to 135 °C. Added JA parameter and its details. Updated Operating Conditions: Replaced VCC, VCCA with VDD. Added Industrial Temperature Range corresponding to TA parameter. Removed IEE, CIN, RUP parameters and their details. Removed “Electrical Characteristics for F_SEL”. Removed “DC Electrical Characteristics for LVPECL”. Added DC Electrical Characteristics. Updated AC Electrical Characteristics: Removed Note “Refer to Figure 4 on page 4” and its reference. Removed Note “Refer to Figure 2 on page 4” and its reference. Removed Note “Refer to Figure 3 on page 4” and its reference. Updated details in “Min”, “Typ” and “Max” columns corresponding to FOUT parameter. Changed typical value of TR, TF parameter from 550 ps to 500 ps. Added details in “Test Conditions” column corresponding to tDC parameter. Added TLOCK parameter and its details. Updated Recommended Crystal Specifications: Removed “Resonance Type” parameter and its details. Document Number: 001-10229 Rev. *I Page 13 of 15 CY2XP22 Document History Page (continued) Document Title: CY2XP22, Crystal to LVPECL Clock Generator Document Number: 001-10229 Revision ECN Orig. of Change Submission Date *B (cont.) 2700242 KVM / PYRS 04/30/2009 Updated Parameter Measurements: Removed figure “Output Load Test Circuit”. Removed figure “Output Duty Cycle/Pulse Width/Period”. Removed figure “Output Rise/Fall Time and Peak-PeakVoltage Swing”. Added Figure 5. Added Figure 6. Added Figure 7. Added Figure 8. Added Figure 10. Updated Ordering Information: Updated part numbers. Updated to new template. *C 2718898 WWZ 06/15/2009 Minor Change: Post to external web. *D 2767298 KVM 09/22/2009 Updated DC Electrical Characteristics: Replaced IDD with IDDT in “Parameter” column (for terminated outputs). Add IDD parameter and its details (for unterminated outputs). Removed Note “IDD includes approximately 24 mA of current that is dissipated externally in the output termination resistors.” and its reference. Added Note 3 and referred the same note in CIN and CINX parameters. Updated AC Electrical Characteristics: Added 1.0 ns under “Max” column corresponding to TR, TF parameter. Updated details in “Test Conditions” column corresponding to TLOCK parameter. Changed maximum value of TLOCK parameter from 10 ms to 5 ms. Added TLFS parameter and its details. *E 2896121 KVM 03/19/2010 Updated Package Diagram: spec 51-85093 – Changed revision from *A to *B. *F 3219081 BASH 04/07/2011 Changed status from Preliminary to Final. Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Updated Package Diagram: spec 51-85093 – Changed revision from *B to *C. Added Acronyms and Units of Measure. Updated to new template. Completing Sunset Review. *G 4336622 XHT 05/02/2014 Updated Package Diagram: spec 51-85093 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *H 4570097 XHT 11/14/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85093 – Changed revision from *D to *E. *I 6135134 XHT 04/12/2018 Updated to new template. Completing Sunset Review. Document Number: 001-10229 Rev. *I Description of Change Page 14 of 15 CY2XP22 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 001-10229 Rev. *I Revised April 12, 2018 Page 15 of 15