CY2XP304BVI

CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • Period jitter peak-peak 125MHz(max.) = 55 ps • Four low-skew LVPECL outputs • Phase-locked loop (PLL) multiplier select • Serially-configurable multiply ratios • Eight-bit feedback counter and six-bit reference counter for high accuracy • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • High-speed PLL bypass mode to 1.5 GHz • 36-VFBGA, 6 × 8 × 1 mm • 3.3V operation Block Diagram PLL_MULT CLK0 CLK0B CLK1 XIN XOUT SER CLK SER DATA INA INAB CLK_SEL XTAL OSCILLATOR PLL xM 0 1 CLK1B CLK2 CLK2B CLK3 CLK3B Pin Configuration C Y 2 X P 3 0 4 3 6 V F B G A P IN C O N F IG U R A T IO N T O P V IE W C LK 0 C LK 0B 6 CLK 1 CLK 1B C LK 2 CLK 2B CLK 3 C LK 3B 5 VDDA GND T O P V IE W GND GND GND V DDA 4 GND S E R_D A TA V DDB V DDA 3 Xo u t S E R_CL K GND GND VDDB NC 2 Xi n GND GND VDDA 1 VDDB VDDB GND P LL_M U L T CLK _S E L IN A IN A B VDDA A B C D E F G H Cypress Semiconductor Corporation Document #: 38-07589 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2004 CY2XP304 Pin Definitions Pin # A1,B1,G3,G4 A2 A3 A4,B2,C1,C3,C4,F3,F4,G2,G5,B5 A5,H1,H2,H4,H5 A6 B6 C6 D6 E6 F6 G6 H6 B3 B4 D1 E1 F1,G1 H3 Pin Name VDDB XIN XOUT GND VDDA CLK0 CLK0B CLK1 CLK1B CLK2 CLK2B CLK3 CLK3B Reference Crystal Input Reference Crystal Feedback Ground 3.3V Power Supply LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) LVPECL Clock Output LVPECL Clock Output (Complement) Pin Description 3.3V Power Supply for Crystal Driver SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down. HIGH select INA/INAB, Internal PLL is bypassed. LOW select internal PLL Differential Clock Input pair, used in PLL-bypassed mode No Connect Frequency Table PLL_Mult 0 1 M (PLL Multiplier) x16 x8 Example Input Crystal Frequency 25 MHz 31.25 MHz 15.625 MHz CLK[0:3],CLKB[0:3] 400 MHz 500 MHz 125 MHz CY2XP304 Two-Wire Serial Interface Introduction The CY2XP304 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2XP304 is a slave device and can either read or write information on the dataline upon request from the master device. Figure 1 shows the basic bus connections between master and slave device. The buses are shared by a number of devices and are pulled HIGH by a pull-up resistor. Data is allowed to change only at LOW period of clock, and must be stable at the HIGH period of clock. To acknowledge, drive the Sdata LOW before the Sclk rising edge and hold it LOW until the Sclk falling edge. Serial Interface Format Each slave carries an address. The data transfer is initiated by a start signal (S). Each transfer segment is one byte in length. The slave address and the read/write bit are first sent from the master device after the start signal. The addressed slave device must acknowledge (Ack) the master device. Depending on the Read/Write bit, the master device will either write data into (logic 0) or read data (logic 1) from the slave device. Each time a byte of data is successfully transferred, the receiving device must acknowledge. At the end of the transfer, the master device will generate a stop signal (P). Serial Interface Transfer Format Figure 2 shows the serial interface transfer format used with the CY2XP304. Two dummy bytes must be transferred before the first data byte. The CY2XP304 has only three bytes of latches to store information, and the third byte of data is reserved. Extra data will be ignored. Serial Interface Specifications Figure 2 shows the basic transmission specification. To begin and end a transmission, the master device generates a start signal (S) and a stop signal (P). Start (S) is defined as switching the Sdata from HIGH to LOW while the Sclk is at HIGH. Similarly, stop (P) is defined as switching the Sdata from LOW to HIGH while holding the Sclk HIGH. Between these two signals, data on Sdata is synchronous with the clock on the Sclk. Document #: 38-07589 Rev. *B Page 2 of 11 CY2XP304 S d a ta S clk S c lk _ C S d ata _ C Rp Rp V DD S d ata _ C S clk _ in S d ata _ in S clk _ in S d ata _ in M a s te r D e vic e S lav e D ev ice Figure 1. Device Connections S clk S data Start (S) valid data Acknowledge Stop (P) Figure 2. Serial Interface Specifications 1 bit 7 bits Slave Address 1 bit R/W 1 bit 8 bits Dummy Byte 0 1 bit 8 bits 1 bit 8 bits 1 bit S Ack Ack Dummy Byte 1 Ack Data 0 Ack Data 1 8 bits Ack 1 bit P Figure 3. CY2XP304 Transfer Format Serial Interface Address for the CY2XP304 A6 1 A5 1 A4 0 A3 0 A2 1 A1 0 A0 1 R/W 0 Serial Interface Programming for the CY2XP304 b7 Data0 Data1 Data2 QCNTBYP P Reserved b6 SELPQ P Reserved b5 Q P Reserved b4 Q P Reserved b3 Q P Reserved b2 Q P Reserved b1 Q P Reserved b0 Q P Reserved To program the CY2XP304 using the two-wire serial interface, set the SELPQ bit HIGH. The default setting of this bit is LOW. The P and Q values are determined by the following formulas: Pfinal = (P7..0 + 3) * 2 Qfinal = Q5..0 + 2 If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value of 1. The default setting of this bit is LOW. If the SELPQ bit is set LOW, the PLL multipliers will be set using the values in the Select Function Table. CyberClocks™ has been developed to generate P and Q values for stable PLL operation. This software is downloadable from www.cypress.com. Document #: 38-07589 Rev. *B Page 3 of 11 CY2XP304 PLL Frequency = Reference x P/Q = Output Reference Q Φ VCO P Output PLL Figure 4. PLL Block Diagram Functional Specifications Crystal Input The CY2XP304 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 5 of this data sheet. The oscillator circuit requires external capacitors. Please refer to the application note entitled Crystal Oscillator Topics for details. Select Input There are two select input pins, the PLL_MULT and CLK_SEL. PLL_MULT pin selects the frequency multiplier in the PLL, and is a standard LVCMOS input. The S pin has an internal pull-up resistor. The multiplier selection is given on page 2 of this data sheet (see Frequency Table). State Transition Characteristics Specifies the maximum settling time of the CLK and CLKB outputs from device power-up. For VDD and VDDX any sequences are allowed to power-up and power-down the CY2XP304. State Transition Characteristics From To Transition Latency 3 ms Description Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled. VDD/VDD CLK/CLK B Normal X On Document #: 38-07589 Rev. *B Page 4 of 11 CY2XP304 Absolute Maximum Conditions Parameter VCC VCC VTT VIN VOUT LUI TS TA TJ ØJc ØJa ESDh MSL GATES Description Supply Voltage Operating Voltage Output Termination Voltage Input Voltage Output Voltage Latch Up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Assembled die Condition Non-functional Functional Relative to VCC[1] Relative to VCC[1] Relative to VCC[1] Functional Non-functional Functional Non-functional Functional Functional –65 –40 – 11.38 85.83 2000 3 50 –0.3 –0.3 100 +150 +85 150 Min. –0.3 3.135 VCC – 2 VCC + 0.3 VCC + 0.3 Max. 4.6 3.465 Unit V V V V V mA °C °C °C °C/W °C/W V N.A. Ea. Crystal Requirements Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please refer to the application note entitled Crystal Oscillator Topics for details. Crystal Requirements Parameter XF Frequency Description Min. 10 Max. 31.25 Unit MHz DC Electrical Specifications Parameter VDD VIL VIH RPUP tPU Supply voltage Input signal low voltage at pin PLL_MULT Input signal high voltage at pin PLL_MULT Internal pull-up resistance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.135 – 0.65 10 0.05 Max. 3.465 0.35 – 100 500 Unit V V V kΩ ms Operating Conditions Parameter TA Industrial Temperature Note: 1. Where VCC is 3.3V±5% Description Commercial Temperature Min. 0 –40 Max. 70 85 Unit °C °C Document #: 38-07589 Rev. *B Page 5 of 11 CY2XP304 DC Specifications (VCC = 3.3 V ± 5%, Commercial and Industrial temp.) Parameter VDIF VX IIN VOL VOH IEE CIN LIN Description HSTL Differential Input Voltage[2] HSTL Differential Crosspoint Voltage[3] Input Current Output Low Voltage VCC = 3.3V ± 5% Output High Voltage Maximum Quiescent Supply Current without Output Termination Current Input Pin Capacitance Pin Inductance INA, INAB VIN = VX ± 0.2V IOL = –5 mA[4] IOH = –30 mA[4] VCC – 1.995 VCC – 1.25 Condition Min. 0.4 0.68 Max. 1.9 0.9 |150| VCC – 1.5 VCC – 0.7 150 3 1 Unit V V uA V V mA pF nH Clock Input Pair INA, INAB (HSTL differential signals) PECL Outputs CLK[0:3], CLK[0:3]B (PECL differential signals) Supply Current and VBB AC Electrical Specifications–Input Parameter fIN fXTAL,IN fINA_IN CIN,CMOS Description Input frequency with driven reference, crystal inputs Input frequency with crystal input Input Frequency with INA/INAB inputs Input capacitance at PLL_MULT pin[5] Min. 1 10 0 – Max. 133 31.25 1500 10 Unit MHz MHz MHz pF AC Specifications–PECL Clock Outputs CLK[0:3], CLK[0:3]B Parameter fO Vo(P-P) VCMRO tsk(O) tsk(PP) TR,TF DC tDC,ERR Phase Noise BWLOOP Description Output Frequency Differential output voltage (peak-to-peak) Output Common Voltage Range Output-to-output skew Part-to-part output skew Output Rise / Fall time Long-term average output duty cycle Cycle-cycle duty cycle error at x8 with 15.625-MHz input Phase Noise at 10 kHz (x8 mode) @ 125 MHz PLL Loop Bandwidth 400-MHz 50% duty cycle Standard load Differential Operation 400-MHz 50% duty cycle Standard load Differential Operation 400-MHz 50% duty cycle Differential 20% to 80% CLK_SEL = 0 CLK_SEL = 1 fO < 1GHz Conditions Min. 125 0 0.375 Max. 500 1500 – Unit MHz MHz V V ps ps ns % ps dBc kHz (–3 dB) VCC – 1.425 – – – 45 – –107 50 50 150 0.3 55 70 –92 Notes: 2. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. 4. Equivalent to a termination of 50Ω to VTT. 5. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV. Document #: 38-07589 Rev. *B Page 6 of 11 CY2XP304 AC Specifications–PECL Clock Outputs CLK[0:3], CLK[0:3]B (continued) Parameter tJCRMS Description Cycle-to-cycle RMS jitter Conditions At 125-MHz frequency At 400-MHz frequency At 500-MHz frequency tJCPK Cycle-to-cycle jitter (pk-pk) At 125-MHz frequency At 200-MHz frequency, XF = 25 MHz At 400-MHz frequency At 500-MHz frequency tJPRMS Period jitter RMS At 125-MHz frequency At 400-MHz frequency At 500-MHz frequency tJPPK Period jitter (pk-pk) At 125-MHz frequency At 200-MHz frequency, XF = 25 MHz At 400-MHz frequency At 500-MHz frequency tJLT Long term RMS Jitter (P < 20) At 125-MHz frequency At 400-MHz frequency At 500-MHz frequency tJLT Long term RMS Jitter (20 < P < 40) At 125-MHz frequency At 400-MHz frequency At 500-MHz frequency tJLT Long-term RMS Jitter (40 < P < 60) At 125-MHz frequency At 400-MHz frequency At 500-MHz frequency Min. – – – – – – – – – – – – – – – – – – – – – – – Max. 15 10 12 95 65 55 65 6.8 5.6 6.8 55 50 45 50 25 20 25 55 65 55 70 90 65 Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps AC Electrical Specifications–PECL Clock Outputs: PLL Bypass Mode Parameter Vo(P-P) JP TPD Description Conditions Min 0.375 – 280 280 Max – 1.3 650 750 Unit V ps r.m.s. ps ps Differential output voltage (peak-to-peak) Differential PRBS fo < 1.0 GHz Period Jitter Propagation delay (INA/INAB to output) 660 MHz 50% duty cycle Standard load PECL, 660MHz HSTL,