CY2XP311ZXC

THIS SPEC IS OBSOLETE Spec No: 001-59931 Spec Title: CY2XP311, 312.5 MHZ LVPECL CLOCK GENERATOR Replaced by: None CY2XP311 312.5 MHz LVPECL Clock Generator 312.5 MHz LVPECL Clock Generator Features Functional Description ■ One LVPECL output pair ■ Output frequency: 312.5 MHz ■ External crystal frequency: 25 MHz ■ Low RMS phase jitter at 312.5 MHz, using 25-MHz crystal (1.875 MHz to 20 MHz): 0.3 ps (typical) ■ Pb-free 8-pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial and industrial temperature ranges The CY2XP311 is a PLL (phase locked loop) based high performance clock generator. It is optimized to generate 10 GB Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve 0.3 ps typical RMS phase jitter, which meets both 10 GB Ethernet and SONET jitter requirements. The CY2XP311 has a crystal oscillator interface input and one LVPECL output pair. For a complete list of related documentation, click here. Logic Block Diagram XIN External Crystal CRYSTAL OSCILLATOR PHASE DETECTOR VCO /2 CLK CLK# XOUT /25 OE Cypress Semiconductor Corporation Document Number: 001-59931 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 27, 2020 CY2XP311 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Frequency Table ............................................................... 3 Absolute Maximum Conditions ....................................... 4 Operating Conditions ....................................................... 4 DC Electrical Characteristics .......................................... 5 AC Electrical Characteristics .......................................... 6 Recommended Crystal Specifications ........................... 6 Parameter Measurements ................................................ 7 Application Information ................................................... 9 Power Supply Filtering Techniques ............................. 9 Termination for LVPECL Output .................................. 9 Crystal Input Interface ................................................. 9 Document Number: 001-59931 Rev. *F Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Drawing and Dimensions ............................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC® Solutions ...................................................... 14 Cypress Developer Community ................................. 14 Technical Support ..................................................... 14 Page 2 of 14 CY2XP311 Pinouts Figure 1. 8-pin TSSOP pinout VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# OE Pin Definitions 8-pin TSSOP Pin Number Pin Name I/O Type Description 1, 8 VDD Power 3.3 V or 2.5 V power supply. 2 VSS Power Ground 3, 4 XOUT, XIN 5 OE CMOS input 6, 7 CLK#, CLK LVPECL output XTAL output and input Parallel resonant crystal interface Output enable. When HIGH, the output is enabled. When LOW, the output is high impedance Differential clock output Frequency Table Input Crystal Frequency (MHz) PLL Multiplier Value 25 12.5 Document Number: 001-59931 Rev. *F Output Frequency (MHz) 312.5 Page 3 of 14 CY2XP311 Absolute Maximum Conditions Parameter Description Conditions Min Max Unit – –0.5 4.4 V VDD Supply voltage VIN[1] Input voltage, DC Relative to VSS –0.5 VDD + 0.5 V TS Temperature, storage Non operating –65 150 C TJ Temperature, junction – – 135 C ESDHBM ESD protection, human body model JEDEC STD 22-A114-B 2000 – V UL–94 Flammability rating At 1/8 in. V–0 JA[2] Thermal resistance, junction to ambient 0 m/s airflow 100 1 m/s airflow 91 2.5 m/s airflow 87 C/W Operating Conditions Parameter VDD TA TPU Description Min Max Unit 3.3 V supply voltage 3.135 3.465 V 2.5 V supply voltage 2.375 2.625 V 0 70 C Ambient temperature, industrial –40 85 C Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms Ambient temperature, commercial Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document Number: 001-59931 Rev. *F Page 4 of 14 CY2XP311 DC Electrical Characteristics Parameter IDD Description Operating supply current with output unterminated IDDT Operating supply current with output terminated Test Conditions Min Typ Max Unit VDD = 3.465 V, OE = VDD, output unterminated – – 125 mA VDD = 2.625 V, OE = VDD, output unterminated – – 120 mA VDD = 3.465 V, OE = VDD, output terminated – – 150 mA VDD = 2.625 V, OE = VDD, output terminated – – 145 mA VOH LVPECL output high voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD – 1.15 – VDD – 0.75 V VOL LVPECL output low voltage VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V VDD – 2.0 – VDD – 1.625 V VOD1 LVPECL peak-to-peak output voltage swing VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD – 2.0 V 600 – 1000 mV VOD2 LVPECL output voltage swing (VOH – VOL) VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V 500 – 1000 mV VOCM LVPECL output common mode voltage (VOH + VOL)/2 VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V 1.2 – – V IOZ LVPECL output leakage current Output off, OE = VSS –35 – 35 A VIH Input high voltage, OE Pin – 0.7 × VDD – VDD + 0.3 V VIL Input low voltage, OE Pin – –0.3 – 0.3 × VDD V IIH Input high current, OE Pin OE = VDD – – 115 µA Input low current, OE Pin OE = VSS –50 – – µA Input capacitance, OE Pin – – 15 – pF Pin capacitance, XIN & XOUT – – 4.5 – pF IIL CIN [3] CINX[3] Notes 3. Not 100% tested, guaranteed by design and characterization. Document Number: 001-59931 Rev. *F Page 5 of 14 CY2XP311 AC Electrical Characteristics Parameter [4] FOUT TR, TF[5] TJitter() Description Conditions Output frequency [6] Min Typ Max Unit – 312.5 – MHz Output rise or fall time 20% to 80% of full output swing – 0.5 1.0 ns – ps RMS phase jitter (random) 312.5 MHz, (1.875 to 20 MHz) – 0.3 TDC[7] Output duty cycle Measured at zero crossing point 45 – 55 % TOHZ Output disable time Time from falling edge on OE to stopped outputs (Asynchronous) – – 100 ns TOE Output enable time Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – – 100 ns TLOCK Startup time Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) – – 5 ms Min Max Unit Recommended Crystal Specifications Parameter [8] Description Mode Mode of Oscillation Fundamental – F Frequency 25 25 ESR Equivalent Series Resistance – 50  CS Shunt Capacitance – 7 pF MHz Notes 4. Not 100% tested, guaranteed by design and characterization. 5. Refer to Figure 5 on page 7. 6. Refer to Figure 6 on page 7. 7. Refer to Figure 7 on page 8. 8. Characterized using an 18 pF parallel resonant crystal. Document Number: 001-59931 Rev. *F Page 6 of 14 CY2XP311 Parameter Measurements Figure 2. 3.3 V Output Load AC Test Circuit 2V Z = 50 VDD SCOPE CLK 50 LVPECL Z = 50 VSS CLK# 50 -1.3V +/- 0.165V Figure 3. 2.5 V Output Load AC Test Circuit 2V VDD SCOPE Z = 50 CLK Z = 50 CLK# 50 LVPECL VSS 50 -0.5V +/- 0.125V Figure 4. Output DC Parameters VA CLK VOD VOCM = (V A + VB)/2 CLK# VB Figure 5. Output Rise and Fall Time CLK# CLK 80% 80% 20% 20% TR TF Figure 6. RMS Phase Jitter Document Number: 001-59931 Rev. *F Page 7 of 14 CY2XP311 Parameter Measurements (continued) Phase noise Noise Power Phase noise mask Offset Frequency f2 f1 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 8. Output Enable Timing OE VIL TOHZ VIH TOE CLK High Impedance CLK# Document Number: 001-59931 Rev. *F Page 8 of 14 CY2XP311 Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 9 illustrates a typical filtering scheme. 0.01 to 0.1 µF ceramic chip capacitors are located close to the VDD pins to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. An acceptable alternative power supply configuration is shown in Figure 10. Figure 9. Power Supply Filtering 3.3V or 2.5V VDD (Pin 8) VDD (Pin 1) 3.3V 125 125 Z0 = 50 CLK CLK# IN Z0 = 50 84 84 Crystal Input Interface 0.01µF 10µF 3.3V or 2.5V The CY2XP311 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 12 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are therefore layout dependent. Figure 12. Crystal Input Interface XIN 0.01µF 10 VDD (Pin 1) Figure 11. LVPECL Output Termination 0.01µF Figure 10. Alternative Power Supply Filtering VDD (Pin 8) for VDD = 2.5 V operation, or it can be terminated to VDD–1.5 V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 11 shows a standard termination scheme. 0.01µF 10µF X1 18 pF Parallel Crystal C1 33 pF Device XOUT C2 27 pF Termination for LVPECL Output The CY2XP311 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3 V operation, this data sheet specifies output levels for termination to VDD–2.0 V. This same termination voltage can also be used Document Number: 001-59931 Rev. *F Page 9 of 14 CY2XP311 Ordering Information Part Number Package Type Product Flow CY2XP311ZXI 8-pin TSSOP Industrial, –40 C to 85 C CY2XP311ZXIT 8-pin TSSOP – Tape and Reel Industrial, –40 C to 85 C Ordering Code Definitions CY 2X P311 Z X X T X = blank or T blank = Tube; T = Tape and Reel Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: Z = 8-pin TSSOP Part Identifier Family Company ID: CY = Cypress Document Number: 001-59931 Rev. *F Page 10 of 14 CY2XP311 Package Drawing and Dimensions Figure 13. 8-pin TSSOP (4.40 mm Body) Package Outline, 51-85093 51-85093 *E Document Number: 001-59931 Rev. *F Page 11 of 14 CY2XP311 Acronyms Acronym Document Conventions Description Units of Measure CLKOUT Clock Output CMOS Complementary Metal Oxide Semiconductor °C degree Celsius DPM Die Pick Map kHz kilohertz EPROM Erasable Programmable Read Only Memory k kilohm LVDS Low-Voltage Differential Signalling MHz megahertz LVPECL Low-Voltage Positive Emitter Coupled Logic M megaohm NTSC National Television System Committee µA microampere OE Output Enable PAL Phase Alternate Line PD Power Down PLL Phase Locked Loop TTL Transistor-Transistor Logic Document Number: 001-59931 Rev. *F Symbol Unit of Measure µs microsecond µV microvolt µVrms microvolts root-mean-square mA milliampere mm millimeter ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt  ohm ppm parts per million V volt Page 12 of 14 CY2XP311 Document History Page Document Title: CY2XP311, 312.5 MHz LVPECL Clock Generator Document Number: 001-59931 Rev. ECN No. Orig. of Change Submission Date ** 2897143 KVM 03/22/2010 *A 2915328 KVM 04/16/2010 Changed status from Preliminary to Final. *B 3201150 BASH 03/21/2011 Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Updated Package Drawing and Dimensions: spec 51-85093 – Changed revision from *B to *C. Added Acronyms and Units of Measure. *C 4335323 CINM 04/07/2014 Updated Package Drawing and Dimensions: spec 51-85093 – Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *D 4570097 CINM 11/14/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” in the end. Updated Ordering Information: Updated part numbers. Updated Package Drawing and Dimensions: spec 51-85093 – Changed revision from *D to *E. *E 5686604 XHT 04/06/2017 Updated to new template. Completing Sunset Review. *F 6869116 XHT 04/27/2020 Obsolete document. Completing Sunset Review. Document Number: 001-59931 Rev. *F Description of Change New data sheet. Page 13 of 14 CY2XP311 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Clock Tree Services Power Management ICs cypress.com/pmic cypress.com/cts Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2010-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-59931 Rev. *F Revised April 27, 2020 Page 14 of 14