CY2XP31ZXIT

CY2XP31 312.5 MHz LVPECL Clock Generator Features ■ ■ ■ ■ ■ ■ ■ Functional Description The CY2XP31 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, which meets both 10 Gb Ethernet and SONET jitter requirements. The CY2XP31 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL output pair Output frequency: 312.5 MHz External crystal frequency: 25 MHz Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.3 ps (typical) Pb-free 8-Pin TSSOP package Supply voltage: 3.3 V or 2.5 V Commercial and industrial temperature ranges Logic Block Diagram XIN External Crystal XOUT /25 OE CRYSTAL OSCILLATOR PHASE DETECTOR VCO /2 CLK CLK# Pinouts Figure 1. Pin Diagram – 8-Pin TSSOP VDD VSS XOUT XIN Table 1. Pin Definition – 8-Pin TSSOP Pin Number 1, 8 2 3, 4 5 6,7 Pin Name VDD VSS XOUT, XIN OE CLK#, CLK Power Power I/O Type 1 2 3 4 8 7 6 5 VDD CLK CLK# OE Description 3.3 V or 2.5 V power supply. All supply current flows through pin 1 Ground Parallel resonant crystal interface Output enable. When HIGH, the output is enabled. When LOW, the output is high impedance Differential clock output XTAL Output and Input CMOS Input LVPECL Output Cypress Semiconductor Corporation Document #: 001-06385 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 7, 2011 [+] Feedback CY2XP31 Frequency Table Inputs Crystal Frequency (MHz) 25 PLL Multiplier Value 12.5 Output Frequency (MHz) 312.5 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM UL–94 ΘJA[2] Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection, Human Body Model Flammability Rating Thermal Resistance, Junction to Ambient JEDEC STD 22-A114-B At 1/8 in. 0 m/s airflow 1 m/s airflow 2.5 m/s airflow Relative to VSS Non operating Description Conditions Min –0.5 –0.5 –65 – 2000 V–0 100 91 87 °C/W Max 4.4 VDD + 0.5 150 135 – Unit V V °C °C V Operating Conditions Parameter VDD TA TPU 3.3 V Supply Voltage 2.5 V Supply Voltage Ambient Temperature, Commercial Ambient Temperature, Industrial Power-up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) Description Min 3.135 2.375 0 –40 0.05 Max 3.465 2.625 70 85 500 Unit V V °C °C ms Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document #: 001-06385 Rev. *H Page 2 of 10 [+] Feedback CY2XP31 DC Electrical Characteristics Parameter Description Operating Supply Current with IDD Output Unterminated Test Conditions Min VDD = 3.465 V, OE = VDD, output untermi– nated – VDD = 2.625 V, OE = VDD, output unterminated VDD = 3.465 V, OE = VDD, output terminated – – VDD = 2.625 V, OE = VDD, output terminated VDD = 3.3 V or 2.5 V, RTERM = 50Ω to VDD – VDD –1.15 2.0 V VDD = 3.3 V or 2.5 V, RTERM = 50Ω to VDD – VDD –2.0 2.0 V VDD = 3.3 V or 2.5 V, RTERM = 50Ω to VDD – 600 2.0 V 500 VDD = 2.5 V, RTERM = 50Ω to VDD – 1.5 V VDD = 2.5 V, RTERM = 50Ω to VDD – 1.5 V Output off, OE = VSS 1.2 –35 0.7*VDD –0.3 – –50 – – Typ – – – – – – – – – – – – – – 15 4.5 Max 125 120 150 145 VDD –0.75 VDD –1.625 1000 1000 – 35 VDD+0.3 0.3*VDD 115 – – – Unit mA mA mA mA V V mV mV V μA V V µA µA pF pF IDDT VOH VOL VOD1 VOD2 VOCM IOZ VIH VIL IIH IIL CIN[5] CINX[5] Operating Supply Current with Output Terminated LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Peak-to-Peak Output Voltage Swing LVPECL Output Voltage Swing (VOH - VOL) LVPECL Output Common Mode Voltage (VOH + VOL)/2 LVPECL Output Leakage Current Input High Voltage, OE Pin Input Low Voltage, OE Pin Input High Current, OE Pin Input Low Current, OE Pin Input Capacitance, OE Pin Pin Capacitance, XIN & XOUT OE = VDD OE = VSS AC Electrical Characteristics[5] Parameter FOUT TR, TF[3] TJitter(φ)[6] TDC[7] TOHZ TOE TLOCK Description Output Frequency Output Rise or Fall Time RMS Phase Jitter (Random) Output Duty Cycle Output Disable Time Output Enable Time Startup Time Conditions 20% to 80% of full output swing 312.5 MHz, (1.875 to 20 MHz) Measured at zero crossing point Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) Min – – – 45 – – – Typ 312.5 0.5 0.3 – – – – Max – 1.0 – 55 100 100 5 Unit MHz ns ps % ns ns ms Recommended Crystal Specifications[4] Parameter Mode F ESR CS Description Mode of Oscillation Frequency Equivalent Series Resistance Shunt Capacitance Min Max Fundamental 25 25 – 50 – 7 Unit MHz Ω pF Document #: 001-06385 Rev. *H Page 3 of 10 [+] Feedback CY2XP31 Parameter Measurements Figure 2. 3.3 V Output Load AC Test Circuit 2V Z = 50Ω SCOPE CLK 50Ω Z = 50Ω CLK# 50Ω -1.3V +/- 0.165V VDD LVPECL VSS Figure 3. 2.5 V Output Load AC Test Circuit 2V Z = 50Ω SCOPE CLK 50Ω Z = 50Ω CLK# 50Ω -0.5V +/- 0.125V VDD LVPECL VSS Figure 4. Output DC Parameters CLK VOD CLK# VA VOCM = (V A + VB)/2 VB Figure 5. Output Rise and Fall Time CLK# 20% TR 80% 80% 20% TF CLK Notes 3. Refer to Figure 5 on page 4. 4. Characterized using an 18 pF parallel resonant crystal. 5. Not 100% tested, guaranteed by design and characterization. 6. Refer to Figure 6 on page 5. 7. Refer to Figure 7 on page 5. Document #: 001-06385 Rev. *H Page 4 of 10 [+] Feedback CY2XP31 Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mask Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 8. Output Enable Timing OE VIL VIH TOHZ CLK TOE High Impedance CLK# Document #: 001-06385 Rev. *H Page 5 of 10 [+] Feedback CY2XP31 Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 9 illustrates a typical filtering scheme. Because all of the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. Figure 9. Power Supply Filtering Figure 10. LVPECL Output Termination 3.3V 125Ω Z0 = 50Ω 125Ω CLK Z0 = 50Ω 84Ω 84Ω IN CLK# V DD (Pin 8) 3.3V 0.1μF 0.01 µF 10µ F Crystal Input Interface The CY2XP31 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 11 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are therefore layout dependent. Figure 11. Crystal Input Interface VDD (Pin 1) Termination for LVPECL Output The CY2XP31 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3 V operation, this data sheet specifies output levels for termination to VDD–2.0 V. This same termination voltage can also be used for VDD = 2.5 V operation, or it can be terminated to VDD-1.5 V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 10 shows a standard termination scheme. X1 18 pF Parallel Crystal C1 33 pF XIN Device XOUT C2 27 pF Document #: 001-06385 Rev. *H Page 6 of 10 [+] Feedback CY2XP31 Ordering Information Part Number Package Type Product Flow CY2XP31ZXC CY2XP31ZXCT CY2XP31ZXI CY2XP31ZXIT 8-Pin TSSOP 8-Pin TSSOP – Tape and Reel 8-Pin TSSOP 8-Pin TSSOP – Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to 85°C Industrial, -40°C to 85°C Ordering Code Definitions CY xx xxx Z X C/I T T = Tape and Reel Temperature Range: C = Commercial, I = Industrial Pb-free Package Type Part Identifier Family Company ID: CY = Cypress Package Drawing and Dimensions Figure 12. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 51-85093 *C Document #: 001-06385 Rev. *H Page 7 of 10 [+] Feedback CY2XP31 Acronyms Table 2. Acronyms Used Acronym Description Document Conventions Table 3. Units of Measure Symbol Unit of Measure CLKOUT CMOS DPM EPROM LVDS LVPECL NTSC OE PAL PD PLL PPM TTL Clock output Complementary metal oxide semiconductor Die pick map Erasable programmable read only memory Low-voltage differential signaling Low voltage positive emitter coupled logic National television system committee Output enable Phase alternate line Power-down Phase locked loop Parts per million Transistor transistor logic °C kHz kΩ MHz MΩ µA µs µV µVrms mA mm ms mV nA ns nV Ω degrees Celsius kilohertz kilohms megahertz megaohms microamperes microseconds microvolts microvolts root-mean-square milliamperes millimeters milliseconds millivolts nanoamperes nanoseconds nanovolts ohms Document #: 001-06385 Rev. *H Page 8 of 10 [+] Feedback CY2XP31 Document History Page Document Title: CY2XP31 312.5 MHz LVPECL Clock Generator Document Number: 001-06385 Revision ECN Orig. of Change Submission Date Description of Change ** *A *B 422680 506198 1337067 RGL RGL JWK / KVM /ARI See ECN See ECN See ECN New data sheet Supplied values in TBDs, Change status from Advance Information to Preliminary Changed VCC* to VDD*, VEE to VSS, Gave pins 1 and 8 the same name (VDD), Added MSL and CIN specifications, Removed pull up from pin 5, Changed VIL, VIH, IIH, IDD, IDDA, VOH, VOL, tR and tF specifications, Added commercial temperature, Changed supply filtering recommendations Removed alternate termination figure, Cleaned up several drawings Fixed cross references and edited data sheet for template compliance, Title change Changed crystal frequency to 25 MHz only; removed other frequencies; output frequencies adjusted accordingly, Changed phase jitter value, Removed MSL spec Changed IIL and IIH values, Changed rise / fall time value from 350 ps to 500 ps Changed max junction temp from 125°C to 135°C, Added thermal resistance Clarified that IDD is with outputs loaded, Changed Data Sheet Status to Final. Typos: changed VCC to VDD OE pin capacitance changed from 7pF to 15pF Changed IDD footnote Reformatted AC & DC tables Added specs CINX and IOZ Added OE timing, and startup timing Added OE waveforms Added IDD for 2.5 V Changed footnote about external power dissipation No change. Submit to ECN for product launch. Add IDD spec for unterminated outputs Change parameter name for IDD (terminated outputs) from IDD to IDDT Remove IDD footnote about externally dissipated current Add footnote reference to CIN and CINX:not 100% tested Add max limit for TR, TF: 1.0 ns Change TLOCK max from 10 ms to 5 ms Updated Package Diagram (Figure 12) Template and style updates as per current Cypress standards. Added ordering code definitions, acronyms, and units of measure. Updated package diagram to *C. *C 2669117 KVM/ AESA 03/05/2009 *D 2700242 KVM/PYRS 04/30/2009 *E *F 2718433 2767308 WWZ/HMT KVM 06/12/2009 09/22/2009 *G *H 2896121 3219081 KVM BASH 03/19/2010 04/07/2011 Document #: 001-06385 Rev. *H Page 9 of 10 [+] Feedback CY2XP31 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06385 Rev. *H Revised April 7, 2011 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback