CY2XP41_11

CY2XP41 Crystal to LVPECL Clock Generator Features ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY2XP41 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate high performance clock frequencies for DVD-R applications. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets application jitter requirements. The CY2XP41 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL output pair External crystal frequency: 25.0 MHz Selectable output frequency: 62.5 MHz or 75 MHz Low RMS phase jitter at 75 MHz, using 25 MHz crystal (1.5 MHz–10 MHz): 0.27 ps (typical) Low RMS phase jitter at 62.5 MHz, using 25 MHz crystal (1.5 MHz–10 MHz): 0.38 ps (typical) Pb-free 8-Pin TSSOP package Supply voltage: 3.3 V Commercial temperature range Logic Block Diagram XIN External Crystal XOUT FS Crystal Oscillator PLL CLK CLK# Cypress Semiconductor Corporation Document #: 001-48923 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2011 [+] Feedback CY2XP41 Contents Pinouts .............................................................................. 3 Absolute Maximum Conditions ....................................... 4 Operating Conditions ....................................................... 4 Electrical Characteristics for Input ................................. 4 DC Electrical Characteristics for Power Supplies ......... 4 Frequency Table ............................................................... 4 DC Electrical Characteristics for LVPECL Output ......... 5 Crystal Characteristics .................................................... 5 Measurement Definitions ................................................. 6 Application Information ................................................... 7 Power Supply Filtering Techniques ............................. 7 Termination for LVPECL Output .................................. 7 Crystal Interface .......................................................... 7 Ordering Information ........................................................ 8 Acronyms .......................................................................... 9 Document Conventions ................................................... 9 Document History Page ................................................. 10 Sales, Solutions, and Legal Information ...................... 10 Worldwide Sales and Design Support ....................... 10 Products .................................................................... 10 PSoC Solutions ......................................................... 10 Document #: 001-48923 Rev. *C Page 2 of 10 [+] Feedback CY2XP41 Pinouts Figure 1. Pin Diagram – 8 Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# FS Table 1. Pin Definitions – 8 Pin TSSOP Pin 1, 8 2 3, 4 5 6,7 Name VDD VSS XOUT, XIN FS CLK#, CLK Power Power XTAL output and input LVCMOS/LVTTL input LVPECL output Type Ground Parallel resonant crystal interface Frequency Select Input, See “Frequency Table” on page 4 Differential Clock Output Description 3.3 V power supply. All supply current flows through pin 1 Document #: 001-48923 Rev. *C Page 3 of 10 [+] Feedback CY2XP41 Frequency Table Input Input Xtal Frequency (MHz) 25 25 FS 0 1 Output Frequency (MHz) 62.5 75.0 Absolute Maximum Conditions Parameter VDD VIN[1.] TS TJ ESDHBM UL–94 ΘJA[2] Description Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) JEDEC STD 22-A114-B Flammability Rating Thermal Resistance, Junction to Ambient At 1/8 in. 0 m/s airflow 1 m/s airflow 2.5 m/s airflow Relative to VSS Non Functional Condition Min –0.5 –0.5 –65 – 2000 V–0 100 91 87 °C/W Max 4.4 VDD + 0.5 150 135 – Unit V V °C °C V Operating Conditions Parameter VDD TA TPU 3.3 V Supply Voltage Ambient Temperature, Commercial Power up time for all VDD to reach minimum specified voltage (ensure power ramps are monotonic) Description Min 3.135 0 0.05 Max 3.465 70 500 Unit V °C ms Electrical Characteristics for Input Parameter VIL VIH IIL IIH CIN[3] CINX[3] Description Input Low Voltage , FS Input High Voltage, FS Input Low Current , FS Input High Current, FS Input Capacitance, FS Input Capacitance, XIN & XOUT FS = VSS FS = VDD Test Conditions Min – 0.7*VDD –50 – – – Typ – – – – 15 4.5 Max 0.3*VDD – – 115 – – Unit V V µA µA pF pF DC Electrical Characteristics for Power Supplies Parameter IDD IDDT Description Power Supply Current with output unterminated Power Supply Current with output terminated Min – – Typ – – Max 125 180 Unit mA mA Note 1. The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model. 3. Not 100% tested, guaranteed by design and characterization. Document #: 001-48923 Rev. *C Page 4 of 10 [+] Feedback CY2XP41 DC Electrical Characteristics for LVPECL Output Parameter VCM VPP Description Common-Mode Voltage (CLK + CLK#) / 2, defined in Figure 5 on page 6, using Figure 2 on page 6 circuit. Differential Peak Output Voltage, defined in Figure 5 on page 6, using Figure 2 on page 6 circuit. Min 175 350 Typ – 780 Max 2000 850 Unit mV mV Crystal Characteristics Parameter Mode of Oscillation F ESR CL CS DL Frequency Equivalent Series Resistance Crystal Load Capacitance Shunt Capacitance Crystal Drive Level – – – – – Description Min Typ Fundamental 25 – 10 – – – 50 – 7 300 MHz Ω pF pF μW Max Unit AC Characteristics[3] Parameter FOUT TR, TF TJitter(φ) TDC TLOCK TLFS Description Output Frequency Output Rise/Fall time RMS Phase Jitter (Random) Duty Cycle Startup Time Re-lock Time Defined in Figure 5 on page 6 75 MHz, (1.5 MHz - 10 MHz filter), 3.3 V 62.5 MHz, (1.5 MHz - 10 MHz filter), 3.3 V Defined in Figure 4 on page 6 Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) Time for CLK to reach valid frequency from FS pin change Test Conditions Min 62.5 – – – 45 – – Typ – 0.35 0.27 0.38 – – – Max 75.0 1.0 – – 55 5 1 Unit MHz ns ps ps % ms ms Document #: 001-48923 Rev. *C Page 5 of 10 [+] Feedback CY2XP41 Measurement Definitions Figure 2. Output Load AC Test Circuit 3.3 V 110Ω CLK CLK# Z=50Ω Z=50Ω 62Ω 3.3 V 110Ω Measurement Point 62Ω 2pF 2pF Figure 3. RMS Phase Jitter Noise Power Phase Noise Phase Noise Mask 40 dB/Decade 20 dB/Decade 1.5 MHz 10 MHz Offset Frequency RMS Jitter = v Area Under the Masked Phase Noise Plot Figure 4. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 5. Output Rise and Fall Time and Peak-Peak Voltage Swing CLK 80% VPP CLK# 20% TR VSS TF VCM Document #: 001-48923 Rev. *C Page 6 of 10 [+] Feedback CY2XP41 Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins degrades performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 6. shows a typical filtering scheme. Since all of the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor shouldbe located in the vicinity of this device, and may be shared with other devices. Figure 6. Power Supply Filtering V DD (Pin 8) 3.3V 0.1μF 0.01 µF 10µF Crystal Interface The CY2XP41 is characterized with 10 pF parallel resonant crystals. The capacitor values shown in Figure 7. are determined using a 25 MHz 10 pF parallel resonant crystal and are chosen to minimize the ppm error. Cypress recommends the following C1 and C2 values: C1 = C2 = 6.8 pF. Figure 7. Crystal Input Interface XIN External Crystal C1 XOUT C2 VDD (Pin 1) Termination for LVPECL Output The CY2XP41 implements its LVPECL driver with a current steering design. For proper operation, it requires resistor termination. This datasheet specifies a termination voltage of VDD–2.1 V. Impedance matching is advised for best signal integrity. Figure 2 on page 6 shows a termination scheme that is recommended as a guideline. Other suitable clock layouts exist and it is recommended that the board designers simulate to guarantee compatibility across all printed circuit and process variations. The recommended termination is a 40Ω load, which is used to achieve the specified common mode and peak-to-peak voltage swing. For optimal signal integrity, traces should also be 40Ω. The device will also operate with 50Ω termination, but is not specified with such a load. Document #: 001-48923 Rev. *C Page 7 of 10 [+] Feedback CY2XP41 Ordering Information Part Number Package Type Product Flow CY2XP41ZXC CY2XP41ZXCT 8-Pin TSSOP 8-Pin TSSOP–Tape and Reel Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Ordering Code Definitions CY 2XP41 ZX C/I T Tape and reel C = Commercial I = Industrial 8-pin Pb-free TSSOP package Base part number Company ID: CY = Cypress Document #: 001-48923 Rev. *C Page 8 of 10 [+] Feedback CY2XP41 Package Drawing and Dimensions Figure 8. 8-Pin Thin Shrunk Small Outline Package (4.40mm Body) Z8 51-85093-*C Acronyms Acronym Description Document Conventions Units of Measure Symbol Unit of Measure ESD FAE HBM JEDEC LCC LVDS OE PCB PLL RMS XO OTP electrostatic discharge field application engineer human body model joint electron devices engineering council leadless chip carrier Low-voltage differential signaling output enable printed circuit board phase-locked loop root mean square crystal oscillator one-time programmable °C mA mV MHz ms ns pF μA degrees Celsius milliampere millivolts megahertz millisecond nanoseconds picofarads microamperes parts per million picoseconds volts ohms watts ppm ps V Ω W Document #: 001-48923 Rev. *C Page 9 of 10 [+] Feedback CY2XP41 Document History Page Document Title: CY2XP41 Crystal to LVPECL Clock Generator Document Number: 001-48923 Submission Orig. of Revision ECN Date Change ** 2669117 03/05/09 XHT/CXQ/ New data sheet KVM Description of Change *A *B 2718433 2767298 06/12/09 09/22/09 WWZ/HMT KVM *C 3196237 03/14/11 BASH No change. Submit to ECN for product launch. Add IDD spec for unterminated outputs Change parameter name for IDD (terminated outputs) from IDD to IDDT Remove IDD footnote about externally dissipated current Add footnote: not 100% tested; plus corresponding references Add new parameter: CINX Add max limit for TR, TF: 1.0 ns Add new parameters: TLOCK and TLFS Edits to the Application Information text Template updates. Included ordering code defintions, acronyms, and units of measure. Updated package diagram from *A to *C. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-48923 Rev. *C Revised March 15, 2011 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback