CY3130
Warp Enterprise™ VHDL CPLD Software
Features
• VHDL (IEEE 1076 and 1164) high-level language compilers with the following features — Designs are portable across multiple devices and/or EDA environments — Facilitates the use of industry-standard simulation and synthesis tools for board- and system-level design — Support for functions and libraries facilitating modular design methodology — Support for enumerated types, operator overloading, For... Generate statements and Integers • Several design entry methods support high-level and low-level design descriptions — Graphical HDL Block Diagram editor with a library of blocks and a text-to-block conversion utility from Aldec — Aldec Active-HDL™ FSM graphical Finite State Machine editor — Behavioral VHDL (IF...THEN...ELSE; CASE...) — Boolean — Structural VHDL — Designs can include multiple entry methods (but only one HDL) in a single design. • Language Assistant library of VHDL templates • Flow Manager Interface to keep track of complex projects • UltraGen™ Synthesis and Fitting Technology — Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device — User-selectable speed and/or area optimization on a block-by-block basis — Perfectly integrated synthesis and fitting — Automatic selection of optimal flip-flop type (D type/T type) — Automatic pin assignment • Ability to specify timing constraints for all of the Delta39K and PSI devices • Support for all Cypress Programmable Logic Devices — Programmable Serial Interface™ (PSI™) — Delta39K™ CPLDs — Ultra37000™ CPLDs — FLASH370i™ CPLDs — MAX340™ CPLDs — Industry standard PLDs (16V8, 20V8, 22V10) • • • • • • • VHDL or Verilog timing model output for use with third-party simulators • Timing simulation provided by Active-HDL™ Sim Release 4.1 from Aldec — Graphical waveform simulator — Graphical entry and modification of all waveforms — Ability to compare waveforms and highlight differences before and after a design change — Ability to probe internal nodes — Display of inputs, outputs, and high-impedance (Z) signals in different colors — Automatic clock and pulse creation — Support for buses — Unlimited simulation time • Architecture Explorer and Dynamic Timing Simulator for PSI and Delta39K devices: — Graphical representation of exactly how your design will be implemented on your specific target device — Zoom from the device level down to the macrocell level — Determine the timing for any path and view that path on a graphical representation of the chip Static Timing Report for all devices Source-Level Behavioral Simulation and Debugger from Aldec Testbench Generation C3ISR Programming Cable Delta39K\Ultra37000 prototype board with a CY37256V 160-pin TQFP device and a CY39100V 208-pin PQFP device On-line documentation and help
Functional Description
Warp Enterprise™ is an integration of the Warp Professional™ CPLD Development package with additional sophisticated EDA software features from Aldec. In addition to accepting IEEE 1076/1164 VHDL text and graphical finite state machines for design entry, Warp Enterprise VHDL provides a graphical HDL block diagram editor with a library of graphical HDL blocks pre-optimized for Cypress devices. Plus, it provides a utility to convert HDL text into graphical HDL blocks. Warp Enterprise synthesizes and optimizes the entered design, and outputs a JEDEC or Intel® hex file for the desired PLD or CPLD (see Figure 1). For simulation, Warp Enterprise provides a timing simulator, a source-level behavioral simulator, as well as VHDL and Verilog timing models for use with third party simulators. Warp Enterprise also provides the designer with important productivity tools such as a testbench generation wizard and the Architecture Explorer graphical analysis tool.
Cypress Semiconductor Corporation Document #: 38-03050 Rev. *C
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3901 North First Street
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San Jose, CA 95134 • 408-943-2600 Revised August 18, 2003
CY3130
The VHDL language also allows users to define their own functions. User-defined functions allow users to extend the capabilities of the language and build reusable files of tested routines. VHDL provides control over the timing of events or processes. It has constructs that identify processes as either sequential, concurrent, or a combination of both. This feature is essential when describing the interaction of complex state machines. VHDL is a rich programming language. Its flexibility reflects the nature of modern digital systems and allows designers to create accurate models of digital designs. Because it is not a verbose language it is easy to learn and compile. In addition, models created in VHDL can readily be transported to other EDA Environments. Warp Enterprise VHDL supports IEEE 1076/1164 VHDL including loops, for/generate statements, full hierarchical designs with packages, enumerated types, and integers.
DESIGN ENTRY
VHDL text
Graphical HDL Blocks
State Machine
Source-Level Simulation
COMPILATION
UltraGen™ Synthesis and Fitting
A VHDL Design Example
Design Entry
VERFICA TION Programming File VHDL, Verilog &Third-Party
Simulation Models
Timing Simulator
Figure 1. Warp® Design Flow VHDL Compiler VHDL is a powerful, industry-standard language for behavioral design entry and simulation, and is supported by all major vendors of EDA tools. It allows designers to learn a single language that is useful for all facets of the design process. VHDL offers designers the ability to describe designs at many different levels. At the highest level, designs can be entered as a description of their behavior. This behavioral description is not tied to any specific target device. As a result, simulation can be done very early in the design to verify correct functionality, which significantly speeds the design process. The Warp syntax for VHDL includes support for intermediate level entry modes such as state tables and Boolean entry. At the lowest level, designs can be described using gate-level descriptions. Warp Enterprise gives the designer the flexibility to intermix all of these entry modes. In addition, VHDL allows you to design hierarchically, building up entities in terms of other entities. This feature allows you to work either “top-down” (designing the highest levels of the system and its interfaces first, then progressing to greater and greater detail) or “bottom-up” (designing elementary building blocks of the system, then combining these to build larger and larger parts) with equal ease. Because this language is an IEEE standard, multiple vendors offer tools for design entry and simulation at both high and low levels and synthesis of designs to different silicon targets. The use of device-independent behavioral design entry gives users the freedom to easily migrate to high volume technologies. The wide availability of VHDL tools provides complete vendor independence as well. Designers can begin their project using Warp Enterprise for Cypress CPLDs and convert to high-volume ASICs using the same VHDL behavioral description with industry-standard synthesis tools.
Warp Enterprise descriptions specify: • The behavior or structure of a design. • The mapping of signals in a design to the pins of a PLD/CPLD (optional). The part of a Warp Enterprise description that specifies the behavior or structure of the design is called an entity/architecture pair. Entity/architecture pairs, as their name implies, are divided into two parts: an entity declaration, which declares the design’s interface signals (i.e., defines what external signals the design has, and what their directions and types are), and a design architecture, which describes the design’s behavior or structure. The entity portion of a design file is a declaration of what a design presents to the outside world (the interface). For each external signal, the entity declaration specifies a signal name, a direction and a data type. In addition, the entity declaration specifies a name by which the entity can be referenced in a design architecture. This section shows code segments from five sample design files. The top portion of each example features the entity declaration. Behavioral Description The architecture portion of a design file specifies the function of the design. As shown in Figure 1, multiple design-entry methods are supported in Warp Enterprise. A behavioral description in VHDL often includes well known constructs such as If...Then...Else, and Case statements. Here is a code segment from a simple state machine design (soda vending machine) that uses behavioral VHDL to implement the design: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY drink IS PORT (nickel,dime,quarter,clock:#in std_logic; returnDime,returnNickel,giveDrink:out std_logic); END drink;
Document #: 38-03050 Rev. *C
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ARCHITECTURE fsm OF drink IS TYPE drinkState IS (zero,five,ten,fifteen, twenty,twentyfive,owedime); SIGNAL drinkstatus:drinkState; BEGIN PROCESS BEGIN WAIT UNTIL clock = ’1’; giveDrink
