Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
General Description
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible[1]
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both
design and manufacturing flows, thereby reducing costs. The
ISR feature provides the ability to reconfigure the devices
without having design changes cause pinout or timing
changes. The Cypress ISR function is implemented through a
JTAG-compliant serial interface. Data is shifted in and out
through the TDI and TDO pins, respectively. Because of the
superior routability and simple timing model of the Ultra37000
devices, ISR allows users to change existing logic designs
while simultaneously fixing pinout assignments and
maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO connections provide the
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3V the output levels
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
— Simplifies design migration
Ultra37000V 3.3V Devices
— Same pinout for 3.3V and 5.0V devices
Devices operating with a 3.3V supply require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
BGA, and Fine-Pitch BGA packages
— Lead (Pb)-free packages available
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
Cypress Semiconductor Corporation
Document #: 38-03007 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 7, 2004
Ultra37000 CPLD Family
Selection Guide
5.0V Selection Guide
General Information
Speed (tPD)
I/O Pins
Speed (fMAX)
Device
Macrocells
Dedicated Inputs
CY37032
32
5
32
6
200
CY37064
64
5
32/64
6
200
CY37128
128
5
64/128
6.5
167
CY37192
192
5
120
7.5
154
CY37256
256
5
128/160/192
7.5
154
CY37384
384
5
160/192
10
118
CY37512
512
5
160/192/264
10
118
Speed Bins
Device
200
167
CY37032
X
X
X
CY37064
X
X
X
CY37128
154
143
125
X
100
X
83
66
X
CY37192
X
X
X
CY37256
X
X
X
CY37384
X
X
CY37512
X
X
X
Device-Package Offering and I/O Count
Device
44Lead
TQFP
44Lead
PLCC
CY37032
37
37
CY37064
37
37
44Lead
CLCC
84Lead
PLCC
37
69
CY37128
84Lead
CLCC
100Lead
TQFP
160Lead
TQFP
160Lead
CQFP
208Lead
PQFP
133
208Lead
CQFP
292Lead
PBGA
388Lead
PBGA
69
69
69
69
133
CY37192
125
CY37256
133
165
197
CY37384
165
197
CY37512
165
165
197
269
3.3V Selection Guide
General Information
Device
Macrocells
Dedicated Inputs
I/O Pins
Speed (tPD)
Speed (fMAX)
CY37032V
32
5
32
8.5
143
CY37064V
64
5
32/64
8.5
143
CY37128V
128
5
64/80/128
10
125
CY37192V
192
5
120
12
100
CY37256V
256
5
128/160/192
12
100
CY37384V
384
5
160/192
15
83
CY37512V
512
5
160/192/264
15
83
Document #: 38-03007 Rev. *E
Page 2 of 64
Ultra37000 CPLD Family
Speed Bins
Device
200
167
154
143
CY37032V
X
CY37064V
X
125
100
83
66
X
X
CY37128V
X
X
CY37192V
X
X
CY37256V
X
X
CY37384V
X
X
CY37512V
X
X
CY37032V
37
CY37064V
37
400Lead
FBGA
Device
44Lead
TQFP
44Lead
CLCC
48Lead
FBGA
84Lead
CLCC
100Lead
TQFP
100Lead
FBGA
160Lead
TQFP
160Lead
CQFP
208Lead
PQFP
208Lead
CQFP
292Lead
PBGA
256Lead
FBGA
388Lead
PBGA
Device-Package Offering and I/O Count
37
37
37
CY37128V
69
69
69
69
85
133
CY37192V
125
CY37256V
133
165
197
CY37384V
165
197
CY37512V
165
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The PIM consists of a completely global routing matrix for
signals from I/O pins and feedbacks from the logic blocks. The
PIM provides extremely robust interconnection to avoid fitting
and density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also
improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing
specifications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp® and third-party development packages
automatically route designs for the Ultra37000 family in a
matter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
Document #: 38-03007 Rev. *E
133
165
197
197
269
269
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Four of the remaining
seven product terms in the logic block are output enable (OE)
product terms. Each of the OE product terms controls up to
eight of the 16 macrocells and is selectable on an individual
macrocell basis. In other words, each I/O cell can select
between one of two OE product terms to control the output
buffer. The first two of these four OE product terms are
available to the upper half of the I/O macrocells in a logic block.
The other two OE product terms are available to the lower half
of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
Page 3 of 64
Ultra37000 CPLD Family
2
3
0−16
PRODUCT
TERMS
7
0−16
PRODUCT
TERMS
FROM
PIM
36
72 x 87
PRODUCT TERM
ARRAY
80
MACROCELL
1
I/O
CELL
0
to cells
2, 4, 6 8, 10, 12
PRODUCT
TERM
ALLOCATOR
0−16
PRODUCT
TERMS
0−16
TO
PIM
MACROCELL
0
2
16
PRODUCT
TERMS
MACROCELL
14
I/O
CELL
14
MACROCELL
15
8
Figure 1. Logic Block with 50% Buried Macrocells
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator
provides two important capabilities without affecting performance: product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Ultra37000 devices,
product terms are steered on an individual basis. Any number
between 0 and 16 product terms can be steered to any
macrocell. Note that 0 product terms is useful in cases where
a particular macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator
allows sharing across groups of four output macrocells in a
Document #: 38-03007 Rev. *E
variable fashion. The software automatically takes advantage
of this capability—the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
worst-case steering and sharing configurations have been
incorporated in the timing specifications for the Ultra37000
devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously
reset at the logic block level with the separate set and reset
product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset
based on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global
synchronous clocks and a product term clock are available to
clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as
well as rising edges (see the Clocking section). Clock polarity
is chosen at the logic block level.
Page 4 of 64
Ultra37000 CPLD Family
Bus Hold Capabilities on all I/Os
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface applications. Bus-hold additionally allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application
note Understanding Bus-Hold—A Feature of Cypress CPLDs.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many applications.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
I/O MACROCELL
FROM PTM
FAST
0
1
0−16
PRODUCT
TERMS
SLEW
SLOW
C25
P
D/T/L
0
1
2
3
C26
0
O
O
0
1
Q
1
R
4
C4
DECODE
C0 C1 C24
I/O CELL
O
“0”
“1”
0
1
2
3
O
C6 C5
1
0
C2 C3
BURIED MACROCELL
FROM PTM
0−16
0
1
PRODUCT
TERMS
C25
0
0
0
1
2
3
O
1
P
D/T/L
C7
Q
R
4
C0 C1 C24
O
1
Q
DECODE
1
0
C2 C3
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
ASYNCHRONOUS
BLOCK RESET
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
ASYNCHRONOUS
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
OE0 OE1
Figure 2. I/O and Buried Macrocells
Document #: 38-03007 Rev. *E
Page 5 of 64
Ultra37000 CPLD Family
INPUT PIN
D
0
1
2
3
FROM CLOCK
POLARITY MUXES
D
Q
0
1
2
3
Q
O
TO PIM
O
C12 C13
C10 C11
D
Q
LE
Figure 3. Input Macrocell
0
TO CLOCK MUX ON
ALL INPUT MACROCELLS
O
1
INPUT/CLOCK PIN
C12
0
O
1
FROM CLOCK
POLARITY INPUT
CLOCK PINS
D
0
1
2
3
Q
D
Q
C13, C14, C15
0
1
2
3
O
TO PIM
O
TO CLOCK MUX
IN EACH
LOGIC BLOCK
OR C16
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
C10C11
C8 C9
D
Q
LE
Figure 4. Input/Clock Macrocell
Clocking
Timing Model
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used.
Figure 5 illustrates the true timing model for the 167-MHz
devices in high speed mode. For combinatorial paths, any
input to any output incurs a 6.5-ns worst-case delay regardless
of the amount of logic used. For synchronous systems, the
input set-up time to the output macrocells for any input is 3.5
ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless
of the logic used.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are designated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
Document #: 38-03007 Rev. *E
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
Page 6 of 64
Ultra37000 CPLD Family
resources for pinout flexibility, and a simple timing model for
consistent system performance.
COMBINATORIAL SIGNAL
tPD = 6.5 ns
INPUT
OUTPUT
Warp
REGISTERED SIGNAL
tS = 3.5 ns
D,T,L
O
tCO = 4.5 ns
INPUT
OUTPUT
CLOCK
Figure 5. Timing Model for CY37128
JTAG and PCI Standards
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifications independent of the design.
IEEE 1149.1-compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in Figure 6.
TCK
TDO
JTAG
TAP
CONTROLLER
Bypass Reg.
Boundary Scan
idcode
Usercode
ISR Prog.
Data Registers
Figure 6. JTAG Interface
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
Document #: 38-03007 Rev. *E
Warp Professional contains several additional features. It
provides an extra method of design entry with its graphical
block diagram editor. It allows up to 5 ms timing simulation
instead of only 2 ms. It allows comparison of waveforms before
and after design changes.
Warp Enterprise™
Warp Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simulation as well as a debugger. It has the ability to generate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the Warp for PC, Warp for UNIX, Warp Professional and
Warp Enterprise data sheets on Cypress’s web site
(www.cypress.com).
Third-Party Software
Instruction Register
TMS
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones
pre-optimized for the target device, by implementing logic in
unused memory and by perfect communication between fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulation and analysis.
Warp Professional™
PCI Compliance
TDI
Development Software Support
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
Ultra37000 family of devices. Refer to the third-party software
data sheet or contact your local sales office for a list of
currently supported third-party vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ultra37000 devices are routed to a
connector at the edge of the printed circuit board. The 37000
UltraISR programming cable is then connected between the
parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming
operations to be performed on each of the Ultra37000 devices
in the system. The ISR software then automatically completes
all of the necessary data manipulations required to accomplish
the programming, reading, verifying, and other ISR functions.
For more information on the Cypress ISR Interface, see the
ISR Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through
a file created by the ISR software. Check the Cypress website
for the latest ISR software download information.
Page 7 of 64
Ultra37000 CPLD Family
The third programming option for Ultra37000 devices is to
utilize the embedded controller or processor that already
exists in the system. The Ultra37000 ISR software assists in
this method by converting the device JEDEC maps into the
ISR serial stream that contains the ISR instruction information
and the addresses and data of locations to be programmed.
The embedded controller then simply directs this ISR stream
to the chain of Ultra37000 devices to complete the desired
reconfiguring or diagnostic operations. Contact your local
sales office for information on availability of this option.
Document #: 38-03007 Rev. *E
The fourth method for programming Ultra37000 devices is to
use the same programmer that is currently being used to
program FLASH370i devices.
For all pinout, electrical, and timing requirements, refer to
device data sheets. For ISR cable and software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available on
a wide variety of third-party programmers. All major third-party
programmers (including BP Micro, Data I/O, and SMS) support
the Ultra37000 family.
Page 8 of 64
Ultra37000 CPLD Family
Logic Block Diagrams
CY37032/CY37032V
Clock/
Input Input
1
TDI
TCK
TMS
4
36
LOGIC
BLOCK
A
16 I/Os
I/O0−I/O15
36
PIM
16
16
16
LOGIC
BLOCK
B
Input
Clock/
Input
4
1
4
4
I/O0-I/O15
LOGIC
BLOCK
A
LOGIC
BLOCK
B
I/O16-I/O31
32
TDI
TCK
TMS
JTAG Tap
Controller
Document #: 38-03007 Rev. *E
36
36
16
16
36
16 I/Os
16 I/Os
I/O16−I/O31
16
CY37064/CY37064V
16 I/Os
TDO
JTAGEN
4
4
JTAG Tap
Controller
16
PIM
LOGIC
BLOCK
D
16 I/Os
LOGIC
BLOCK
C
16 I/Os
I/O48-I/O63
36
16
I/O32-I/O47
32
TDO
Page 9 of 64
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
TDI
CY37128/CY37128V
CLOCK
INPUTS INPUTS
1
4
I/O16–I/O31
I/O32–I/O47
I/O28–I/O63
16 I/Os
LOGIC
BLOCK
36
A
16 I/Os
LOGIC
BLOCK
B
16 I/Os
LOGIC
BLOCK
C
16 I/Os
36
PIM
16
LOGIC
BLOCK
D
36
36
16
16
36
36
16
16
36
36
16
16
16 I/Os
LOGIC
BLOCK
16 I/Os
LOGIC
BLOCK
16 I/Os
LOGIC
BLOCK
16 I/Os
G
I/O112–I/O127
I/O96–I/O111
I/O80–I/O95
F
I/O64–I/O79
64
CY37192/CY37192V
Input
1
Clock/
Input
4
4
4
JTAG Tap
Controller
LOGIC
BLOCK
E
TDO
JTAGEN
H
16
64
TDI
TCK
TMS
Controller
TMS
4
INPUT/CLOCK
MACROCELLS
4
INPUT
MACROCELL
I/O0–I/O15
JTAG Tap
TCK
10 I/Os
I/O0–I/O9
LOGIC
BLOCK
A
10 I/Os
I/O10–I/O19
LOGIC
BLOCK
B
10 I/Os
I/O20–I/O29
LOGIC
BLOCK
C
10 I/Os
I/O30–I/O39
LOGIC
BLOCK
D
10 I/Os
I/O40–I/O49
LOGIC
BLOCK
E
10 I/Os
I/O50–I/O59
LOGIC
BLOCK
F
60
36
36
16
16
36
36
16
16
36
36
16
16
36
16
PIM
36
16
36
36
16
16
36
36
16
16
LOGIC
BLOCK
L
10 I/Os
I/O110–I/O119
LOGIC
BLOCK
K
10 I/Os
I/O100–I/O109
LOGIC
BLOCK
J
10 I/Os
I/O90–I/O99
LOGIC
BLOCK
I
10 I/Os
I/O80–I/O89
LOGIC
BLOCK
H
10 I/Os
I/O70–I/O79
LOGIC
BLOCK
G
10 I/Os
I/O60–I/O69
60
TDO
Document #: 38-03007 Rev. *E
Page 10 of 64
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input Input
CY37256/CY37256V
1
4
4
4
12 I/Os
I/O0−I/O11
LOGIC
BLOCK
A
12 I/Os
I/O12−I/O23
LOGIC
BLOCK
B
12 I/Os
I/O24−I/O35
LOGIC
BLOCK
C
12 I/Os
I/O36−I/O47
LOGIC
BLOCK
D
12 I/Os
I/O48−I/O59
LOGIC
BLOCK
E
12 I/Os
I/O60−I/O71
LOGIC
BLOCK
F
12 I/Os
I/O72−I/O83
LOGIC
BLOCK
G
12 I/Os
LOGIC
BLOCK
H
I/O84−I/O95
TDI
TCK
TMS
JTAG Tap
Controller
Document #: 38-03007 Rev. *E
TDO
96
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
PIM
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
LOGIC
BLOCK
P
12 I/Os
I/O180−I/O191
LOGIC
BLOCK
O
12 I/Os
I/O168−I/O179
LOGIC
BLOCK
N
12 I/Os
I/O156−I/O167
LOGIC
BLOCK
M
12 I/Os
I/O144−I/O155
LOGIC
BLOCK
L
12 I/Os
I/O132−I/O143
LOGIC
BLOCK
K
12 I/Os
I/O120−I/O131
LOGIC
BLOCK
J
12 I/Os
I/O108−I/O119
LOGIC
BLOCK
I
12 I/Os
I/O96−I/O107
96
Page 11 of 64
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input Input
CY37384/CY37384V
1
4
4
4
12 I/Os
I/O0−I/O11
LOGIC
BLOCK
AA
12 I/Os
LOGIC
BLOCK
AB
I/O12−I/O23
12 I/Os
I/O24−I/O35
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
12 I/Os
I/O36−I/O47
LOGIC
BLOCK
AE
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
16
PIM
36
16
LOGIC
BLOCK
AF
36
36
16
16
12 I/Os
I/O48−I/O59
LOGIC
BLOCK
AG
36
36
16
16
12 I/Os
I/O60−I/O71
LOGIC
BLOCK
AH
12 I/Os
LOGIC
BLOCK
AI
I/O72−I/O83
LOGIC
BLOCK
AJ
12 I/Os
I/O84−I/O95
LOGIC
BLOCK
AK
LOGIC
BLOCK
AL
TDI
TCK
TMS
36
JTAG Tap
Controller
Document #: 38-03007 Rev. *E
TDO
96
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
LOGIC
BLOCK
BL
LOGIC
BLOCK
BK
12 I/Os
I/O168−I/O191
LOGIC
BLOCK
BJ
12 I/Os
I/O156−I/O179
LOGIC
BLOCK
BI
12 I/Os
I/O144−I/O167
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
12 I/Os
I/O132−I/O155
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
12 I/Os
I/O120−I/O143
LOGIC
BLOCK
BD
12 I/Os
I/O108−I/O131
LOGIC
BLOCK
BC
12 I/Os
I/O96−I/O119
LOGIC
BLOCK
BB
LOGIC
BLOCK
BA
12 I/Os
I/O96−I/O107
96
Page 12 of 64
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
CY37512/CY37512V
Input
Clock/ Input
4
1
4
4
12 I/Os
I/O0−I/O11
LOGIC
BLOCK
AA
12 I/Os
I/O12−I/O23
LOGIC
BLOCK
AB
12 I/Os
I/O24−I/O35
LOGIC
BLOCK
AC
LOGIC
BLOCK
AD
12 I/Os
I/O36−I/O47
LOGIC
BLOCK
AE
LOGIC
BLOCK
AF
12 I/Os
I/O48−I/O59
12 I/Os
I/O60−I/O71
LOGIC
BLOCK
AG
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
LOGIC
BLOCK
AH
36
16
16
LOGIC
BLOCK
AI
16
16
LOGIC
BLOCK
AJ
36
36
16
16
36
36
16
16
36
36
16
16
36
PIM
36
12 I/Os
I/O72−I/O83
LOGIC
BLOCK
AK
12 I/Os
I/O84−I/O95
LOGIC
BLOCK
AL
36
12 I/Os
LOGIC
BLOCK
AM
36
16
16
36
36
I/O108−I/O119
LOGIC
BLOCK
AN
16
16
12 I/Os
I/O120−I/O131
LOGIC
BLOCK
AO
36
36
16
16
LOGIC
BLOCK
AP
36
36
16
16
I/O96−I/O107
12 I/Os
132
TDI
TCK
TMS
36
JTAG Tap
Controller
LOGIC
BLOCK
BP
LOGIC
BLOCK
BO
12 I/Os
I/O252−I/O263
LOGIC
BLOCK
BN
12 I/Os
I/O240−I/O251
LOGIC
BLOCK
BM
12 I/Os
I/O228−I/O239
LOGIC
BLOCK
BL
LOGIC
BLOCK
BK
12 I/Os
I/O216−I/O227
LOGIC
BLOCK
BJ
LOGIC
BLOCK
BI
12 I/Os
I/O204−I/O215
LOGIC
BLOCK
BH
LOGIC
BLOCK
BG
12 I/Os
I/O192−I/O203
LOGIC
BLOCK
BF
LOGIC
BLOCK
BE
12 I/Os
I/O180−I/O191
LOGIC
BLOCK
BD
12 I/Os
I/O168−I/O179
LOGIC
BLOCK
BC
12 I/Os
I/O156−I/O167
LOGIC
BLOCK
BB
12 I/Os
I/O144−I/O155
LOGIC
BLOCK
BA
12 I/Os
I/O132−I/O143
132
TDO
Document #: 38-03007 Rev. *E
Page 13 of 64
Ultra37000 CPLD Family
5.0V Device Characteristics
Maximum Ratings
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Program Voltage............................................. 4.5 to 5.5V
Current into Outputs .................................................... 16 mA
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-up Current..................................................... > 200 mA
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Operating Range[2]
Ambient Temperature[2]
Junction Temperature
Output Condition
VCC
VCCO
0°C to +70°C
0°C to +90°C
5V
5V ± 0.25V
5V ± 0.25V
3.3V
5V ± 0.25V
3.3V ± 0.3V
Industrial
–40°C to +85°C
–40°C to +105°C
5V
5V ± 0.5V
5V ± 0.5V
3.3V
5V ± 0.5V
3.3V ± 0.3V
Military[3]
–55°C to +125°C
–55°C to +130°C
5V
5V ± 0.5V
5V ± 0.5V
3.3V
5V ± 0.5V
3.3V ± 0.3V
Range
Commercial
5.0V Device Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
VCC = Min.
Min. Typ.
IOH = –2.0 mA
VOHZ
Output HIGH Voltage with
Output Disabled[5]
VCC = Max.
(Mil)[4]
V
4.5
V
3.6
V
(Ind/Mil)[6]
3.6
V
IOL = 16 mA (Com’l/Ind)[4]
0.5
V
IOH = 0 µA
VCC = Min.
V
4.2
(Ind/Mil)[6]
IOH = –150 µA
Output LOW Voltage
Unit
V
2.4
IOH = 0 µA (Com’l)[6]
IOH = –100 µA (Com’l)[6]
VOL
Max.
IOH = –3.2 mA (Com’l/Ind)[4] 2.4
IOL = 12 mA
(Mil)[4]
0.5
V
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs[7]
2.0
VCCmax
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs[7]
–0.5
0.8
V
IIX
Input Load Current
VI = GND OR VCC, Bus-Hold Disabled
–10
10
µA
IOZ
Output Leakage Current
VO = GND or VCC, Output Disabled, Bus-Hold Disabled
–50
50
µA
IOS
Output Short Circuit Current[5, 8] VCC = Max., VOUT = 0.5V
–30
–160
mA
IBHL
Input Bus-Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
+75
µA
IBHH
Input Bus-Hold HIGH
Sustaining Current
VCC = Min., VIH = 2.0V
–75
µA
IBHLO
Input Bus-Hold LOW
Overdrive Current
VCC = Max.
+500
µA
IBHHO
Input Bus-Hold HIGH
Overdrive Current
VCC = Max.
–500
µA
VIH
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”
3. TA is the “Instant On” case temperature.
4. IOH = –2 mA, IOL = 2 mA for TDO.
5. Tested initially and after any design or process changes that may affect these parameters.
6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Document #: 38-03007 Rev. *E
Page 14 of 64
Ultra37000 CPLD Family
Inductance[5]
44-Lead 44-Lead 44-Lead 84-Lead 84-Lead 100-Lead 160-Lead 208-Lead
TQFP PLCC CLCC PLCC CLCC TQFP
TQFP
PQFP Unit
Parameter Description Test Conditions
L
Maximum Pin VIN = 5.0V
Inductance at f = 1 MHz
2
5
2
8
5
8
9
11
nH
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CI/O
Input/Output Capacitance
VIN = 5.0V at f = 1 MHz at TA = 25°C
10
pF
CCLK
Clock Signal Capacitance
VIN = 5.0V at f = 1 MHz at TA = 25°C
12
pF
VIN = 5.0V at f = 1 MHz at TA = 25°C
16
pF
CDP
Dual-Function Pins
Endurance
Characteristics[5]
Parameter
N
[9]
Description
Test Conditions
Minimum Reprogramming Cycles
Normal Programming
3.3V Device Characteristics
Maximum Ratings
Conditions[2]
Min.
Typ.
Unit
1,000
10,000
Cycles
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage............................................. 3.0 to 3.6V
Current into Outputs ...................................................... 8 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range[2]
Range
Ambient Temperature[2]
Junction Temperature
VCC[10]
0°C to +70°C
0°C to +90°C
3.3V ± 0.3V
Commercial
Industrial
–40°C to +85°C
–40°C to +105°C
3.3V ± 0.3V
Military[3]
–55°C to +125°C
–55°C to +130°C
3.3V ± 0.3V
3.3V Device Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
VCC = Min.
IOH = –3 mA (Mil)
VOL
Output LOW Voltage
VCC = Min.
Min.
IOH = –4 mA (Com’l)[4]
Unit
V
[4]
IOL = 8 mA (Com’l)[4]
IOL = 6 mA
Max.
2.4
0.5
V
(Mil)[4]
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for
all Inputs[7]
2.0
5.5
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for
all Inputs[7]
–0.5
0.8
V
IIX
Input Load Current
VI = GND OR VCC, Bus-Hold Disabled
–10
10
µA
IOZ
Output Leakage Current
VO = GND or VCC, Output Disabled,
Bus-Hold Disabled
–50
50
µA
IOS
Output Short Circuit Current[5, 8]
VCC = Max., VOUT = 0.5V
–30
–160
mA
IBHL
Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V
+75
IBHH
Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V
–75
IBHLO
Input Bus-Hold LOW Overdrive Current VCC = Max.
µA
µA
+500
µA
Input Bus-Hold HIGH Overdrive Current VCC = Max.
–500
Notes:
9. Dual pins are I/O with JTAG pins.
10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.
µA
IBHHO
Document #: 38-03007 Rev. *E
Page 15 of 64
Ultra37000 CPLD Family
Inductance[5]
Parameter Description
L
Test Conditions
44Lead
TQFP
44Lead
PLCC
44Lead
CLCC
84Lead
PLCC
84Lead
CLCC
100Lead
TQFP
160Lead
TQFP
2
5
2
8
5
8
9
Maximum Pin VIN = 3.3V
Inductance
at f = 1 MHz
208Lead
PQFP Unit
11
nH
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CI/O
Input/Output Capacitance
VIN = 3.3V at f = 1 MHz at TA = 25°C
8
pF
CCLK
Clock Signal Capacitance
VIN = 3.3V at f = 1 MHz at TA = 25°C
12
pF
VIN = 3.3V at f = 1 MHz at TA = 25°C
16
pF
CDP
Dual Functional Pins
[9]
Endurance Characteristics[5]
Parameter
Description
N
Test Conditions
Minimum Reprogramming Cycles
Normal Programming Conditions
[2]
Min.
Typ.
Unit
1,000
10,000
Cycles
AC Characteristics
5.0V AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
5V
OUTPUT
170Ω (COM'L)
236Ω (MIL)
35 pF
INCLUDING
JIG AND
SCOPE
238Ω (COM'L)
319Ω (MIL)
5V
3.0V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
(a)
170Ω (COM'L)
GND
236Ω (MIL)
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