CY62126ESL MoBL®
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
mode reduces power consumption by more than 99 percent
when deselected (CE HIGH). The input and output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE HIGH), the outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or during a write operation (CE LOW and WE
LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
■
Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■
Easy memory expansion with CE, and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP)
Type II package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Functional Description
The CY62126ESL device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
The CY62126ESL is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
For a complete list of related resources, click here.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64 K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A15
A13
A14
A11
Cypress Semiconductor Corporation
Document Number: 001-45076 Rev. *J
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2018
CY62126ESL MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-45076 Rev. *J
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY62126ESL MoBL®
Pin Configuration
44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
Product
CY62126ESL
Range
VCC Range (V) [2]
Industrial 2.2 V–3.6 V and 4.5 V–5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2 (A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
1.3
2
11
16
1
4
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-45076 Rev. *J
Page 3 of 16
CY62126ESL MoBL®
Maximum Ratings
Output current into outputs (low) ................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Ambient temperature
with power applied ..................................... 55 °C to +125 °C
Supply voltage to ground potential [4, 5] .........–0.5 V to 6.0 V
Device
DC voltage applied to outputs
in High Z State [4, 5] .......................................–0.5 V to 6.0 V
CY62126ESL
Range
Ambient
Temperature
Industrial –40 °C to +85 °C
DC input voltage [4, 5] .....................................–0.5 V to 6.0 V
VCC[6]
2.2 V–3.6 V,
and
4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
45 ns
Min
Typ [7]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –0.1 mA
–
–
3.4 [8]
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1 mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1 mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
4.5 < VCC < 5.5
–0.5
–
0.8
GND < VIN < VCC
–1
–
+1
Unit
V
V
V
V
A
IIX
Input leakage current
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fmax = 1/tRC
–
11
16
mA
–
1.3
2.0
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
ISB1 [9]
Automatic CE power down
current – CMOS Inputs
CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only), f = 0 (OE and WE),
VCC = VCC(max)
–
1
4
A
ISB2 [9]
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
1
4
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
9. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-45076 Rev. *J
Page 4 of 16
CY62126ESL MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
28.2
C/W
3.4
C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50 V
3.0 V
5.0 V
Unit
R1
16600
1103
1800
R2
15400
1554
990
RTH
8000
645
639
VTH
1.2
1.75
1.77
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-45076 Rev. *J
Page 5 of 16
CY62126ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
VCC for data retention
[12]
Data retention current
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
VCC = 1.5 V
Min
Typ [11]
Max
Unit
1.5
–
–
V
–
–
3
A
tCDR [13]
Chip deselect to data retention
time
0
–
–
ns
tR [14]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 2. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-45076 Rev. *J
Page 6 of 16
CY62126ESL MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[16]
5
–
ns
–
18
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
[16, 17]
[16]
tLZCE
CE LOW to Low Z
10
–
ns
tHZCE
CE HIGH to High Z [16, 17]
–
18
ns
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power up
–
45
ns
tDBE
BHE / BLE LOW to data valid
–
22
ns
ns
[16]
tLZBE
BHE / BLE LOW to Low Z
5
–
tHZBE
BHE / BLE HIGH to High Z [16, 17]
–
18
ns
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address Hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BHE / BLE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High Z [16, 17]
–
18
ns
10
–
ns
Write Cycle
tLZWE
[18]
WE HIGH to Low Z
[16]
Notes
15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 1 on page 5.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 001-45076 Rev. *J
Page 7 of 16
CY62126ESL MoBL®
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [19, 20]
tRC
RC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATAOUT VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [20, 21]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA I/O
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
19. Device is continuously selected. OE, CE = VIL.
20. WE is high for read cycles.
21. Address valid before or similar to CE transition low.
Document Number: 001-45076 Rev. *J
Page 8 of 16
CY62126ESL MoBL®
Switching Waveforms (continued)
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH during Write) [22, 23]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
DATA I/O
tSD
tHD
DATAIN VALID
NOTE 24
tHZOE
Figure 6. Write Cycle No. 2 (CE Controlled) [22, 23]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 24
tHZOE
Notes
22. Data I/O is high impedance if OE = VIH.
23. If CE goes high simultaneously with WE high, the output remains in high impedance state.
24. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-45076 Rev. *J
Page 9 of 16
CY62126ESL MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [25]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 26
tLZWE
tHZWE
Figure 8. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [25]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 26
tSD
tHD
DATAIN VALID
tLZWE
Notes
25. If CE goes high simultaneously with WE high, the output remains in high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-45076 Rev. *J
Page 10 of 16
CY62126ESL MoBL®
Truth Table
CE [27]
WE
OE
BHE
BLE
H
X
X
X
X
High Z
Deselect or power down
Standby (ISB)
L
X
X
H
H
High Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Inputs/Outputs
Mode
Power
Note
27. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-45076 Rev. *J
Page 11 of 16
CY62126ESL MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62126ESL-45ZSXI
Package Type
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 2
6
E
SL - 45
ZS X
I
Temperature Grade:
I = Industrial
Pb-free
Package Type:
ZS = 44-pin TSOP Type II
Speed Grade: 45 ns
SL = Wide Voltage Range (3 V and 5 V)
Process Technology: E = 90 nm Technology
Bus width: 6 = × 16
Density: 2 = 1-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-45076 Rev. *J
Page 12 of 16
CY62126ESL MoBL®
Package Diagram
Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-45076 Rev. *J
Page 13 of 16
CY62126ESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
WE
Write Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-45076 Rev. *J
Symbol
Unit of Measure
Page 14 of 16
CY62126ESL MoBL®
Document History Page
Document Title: CY62126ESL MoBL®, 1-Mbit (64 K × 16) Static RAM
Document Number: 001-45076
Revision
ECN
Submission
Date
Orig. of
Change
**
2610988
11/21/08
VKN /
PYRS
*A
2718906
06/15/2009
VKN
Post to external web.
*B
2944332
06/04/2010
VKN
Added Contents
Updated Electrical Characteristics (Added Note 9 and referred the same note in
ISB2 parameter).
Updated Truth Table (Added Note 27 and referred the same note in CE column).
Updated Package Diagram.
Updated links in Sales, Solutions, and Legal Information.
*C
3113720
12/17/2010
PRAS
Added Ordering Code Definitions.
*D
3292276
06/24/2011
RAME
Updated
Functional
Description
(Removed
“For
best
practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Data Retention Characteristics (Changed the minimum value of tR
parameter).
Updated to new template.
*E
3503697
01/20/2012
TAVA
Updated Electrical Characteristics (Replaced VI with VIN in Test Conditions of
IIX parameter).
Updated Switching Waveforms.
Updated Package Diagram.
*F
4013949
06/04/2013
MEMJ
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA” for VOH
parameter and added maximum value corresponding to that Test Condition.
Added Note 8 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA”.
Updated Package Diagram:
spec 51-85087 – Changed revision from *D to *E.
*G
4241229
01/09/2014
VINI
Updated to new template.
Completing Sunset Review.
*H
4576448
11/21/2014
VINI
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
*I
4592990
12/10/2014
VINI
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
*J
6013882
01/04/2018 AESATP12 Updated logo and copyright.
Document Number: 001-45076 Rev. *J
Description of Change
New data sheet.
Page 15 of 16
CY62147GN/CY621472GN MoBL®
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-45076 Rev. *J
Revised January 4, 2018
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