CY62127BVLL-55ZI

27BV CY62127BV 64K x 16 Static RAM Features • 2.7V–3.6V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 54 mW (max.) (15 mA) • Low standby power (70 ns, LL version) — 54 µW (max.) (15 µA) • Automatic power-down when deselected — Power down either with CE or BHE and BLE HIGH • Independent control of Upper and Lower Bytes • Available in 44-pin TSOP II (forward) and fBGA Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62127BV is available in standard 44-pin TSOP Type II (forward pinout) and fBGA packages. Functional Description The CY62127BV is a high-performance CMOS Static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption by 99% when deselected. The device enters power-down mode when CE is HIGH or when CE is LOW and both BLE and BHE are HIGH. Logic Block Diagram Pin Configurations TSOP II (Forward) Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 DATA IN DRIVERS A12 A11 A10 A9 A7 A6 A3 A2 A1 A0 64K x 16 RAM Array 1024 X 1024 I/O1–I/O8 I/O9–I/O16 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 38-05155 Rev. ** A4 A5 A8 A13 A14 A15 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC ROW DECODER • SENSE AMPS 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 6, 2001 CY62127BV Pin Configurations (continued) fBGA 1 BLE 2 OE 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC 5 A2 CE I/O 2 I/O4 I/O 5 6 NC I/O1 I/O 3 VCC VSS I/O7 I/O8 NC A B C D E F G H 62127BV–3 I/O9 BHE I/O10 I/O11 VSS VCC I/O12 I/O13 I/O15 I/O14 I/O16 NC NC A8 A15 I/O6 A13 A10 WE A11 Selection Guide 62127BV-55 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 55 20 15 62127BV-70 70 15 15 Units ns mA µA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Industrial Ambient Temperature[2] –40°C to +85°C VCC 2.7V–3.6V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. Document #: 38-05155 Rev. ** Page 2 of 11 CY62127BV Electrical Characteristics Over the Operating Range 62127BV–55, 70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE ≥ VIH VIN ≥ VIH or VIN ≤ VIL, f = fMAX Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f=0 0.5 55 ns 70 ns Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA 2.0 –0.3 –1 –1 Min. 2.2 0.4 VCC + 0.3 0.4 +1 +1 20 15 2 Typ.[3] Max. Unit V V V V µA µA mA mA mA ISB1 ISB2 15 µA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 9 9 Unit pF pF AC Test Loads and Waveforms 3.0V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT R2 1262 Ω R1 1076Ω 3.0V OUTPUT 5 pF INCLUDING JIG AND SCOPE 581 Ω R2 1262 Ω GND Rise Time: 1 V/ns R1 1076 Ω VCC ALL INPUT PULSES 90% 10% 90% 10% Fall Time 1 V/ns (b) 1.62V 62127BV-4 Notes: 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05155 Rev. ** Page 3 of 11 CY62127BV Switching Characteristics[5] Over the Operating Range 62127BV–55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [7] [6, 7] 62127BV–70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 70 60 60 0 0 50 30 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 60 ns ns Description Min. 55 Max. 55 10 55 25 5 20 10 20 0 55 55 5 20 55 45 45 0 0 40 25 0 5 25 45 OE HIGH to High Z CE HIGH to High Z CE LOW to Low Z[7] [6, 7] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to LOW Z [8] [7] [6, 7] Byte Disable to HIGH Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z [6, 7] Byte Enable to End of Write Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZWE is less than tLZWE, and tHZBE is less than tLZBE, for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for further conditions from BHE and BLE. Document #: 38-05155 Rev. ** Page 4 of 11 CY62127BV Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only) Parameter VDR ICCDR tCDR[4] tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC-0.3V, VIN > VCC - 0.3V or, VIN < 0.3V. Conditions[9] Min. 2.0 0.5 0 tRC Typ Max. 3.6 15 Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE 62127BV–5 VDR > 2V 3.0V tR Switching Waveforms Read Cycle No.1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 62127BV-6 Notes: 9. No input may exceed VCC + 0.3V. 10. Device is continuously selected. OE, CE, BHE, BLE = VIL. 11. WE is HIGH for read cycle. Document #: 38-05155 Rev. ** Page 5 of 11 CY62127BV Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11, 12, 13] ADDRESS tRC CE tACE OE BHE, BLE tDBE tLZBE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZBE tHZOE tHZCE DATA VALID tPD 50% ISB 62127BV-7 HIGH IMPEDANCE DATA OUT ICC Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSCE CE tSA tAW BHE, BLE tBW tPWE WE tSD DATA I/O DATA VALID tHD tHA 62127BV-8 Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH. 14. If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05155 Rev. ** Page 6 of 11 CY62127BV Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tPWE tHA OE tHZOE DATA I/O NOTE 15 t SD DATA VALID IN 62127BV-9 t HD Write Cycle No.3 (WE Controlled, OE LOW)[13, 14] tWC ADDRESS tSCE CE tSA WE tAW tPWE tHA tBW BHE, BLE t tHZWE DATA I/O NOTE 15 tSD DATA VALID tLZWE 62127BV-10 HD Note: 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05155 Rev. ** Page 7 of 11 CY62127BV Truth Table CE H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L L H L L H L H BHE X L H L L H L L H I/O1–I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9–I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Mode Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Power Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Standby (ISB) Ordering Information Speed (ns) 55 70 Ordering Code CY62127BVLL-55ZI CY62127BVLL-55BAI CY62127BVLL-70ZI CY62127BVLL-70BAI Package Name Z44 BA48A Z44 BA48A 44-Lead TSOP II 48-Ball Fine Pitch Ball Grid Array (fBGA) 44-Lead TSOP II 48-Ball Fine Pitch Ball Grid Array (fBGA) Package Type Operating Range Industrial Document #: 38-05155 Rev. ** Page 8 of 11 CY62127BV Package Diagrams 48-Ball (7.00 mm x 7.00 mm) FBGA BA48A 51-85096-*D Document #: 38-05155 Rev. ** Page 9 of 11 CY62127BV Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A Document #: 38-05155 Rev. ** Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62127BV Document Title: CY62127BV 64K x 16 Static RAM Document Number: 38-05155 REV. ** ECN NO. 109899 Issue Date 01/10/02 Orig. of Change SZV Description of Change Change from Spec number: 38-01018 to 38-05155 Document #: 38-05155 Rev. ** Page 11 of 11