CY62127DV30L-55ZXI

CY62127DV30 1-Mb (64K x 16) Static RAM Features • Temperature Ranges — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • Very high speed: 45 ns • Wide voltage range: 2.2V to 3.6V • Pin compatible with CY62127BV • Ultra-low active power — Typical active current: 0.85 mA @ f = 1 MHz — Typical active current: 5 mA @ f = fMAX • Ultra-low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • Available in Pb-Free and non Pb-Free 48-ball FBGA and a 44-lead TSOP Type II packages Functional Description[1] The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes . Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 2048 x 512 SENSE AMPS ROW DECODER 10 I/O0–I/O7 I/O8–I/O15 BHE WE CE OE BLE A12 A13 A14 A15 A11 COLUMN DECODER CE Power -Down Circuit BHE BLE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05229 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 19, 2006 CY62127DV30 Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range (V) Product Min. Typ. Max. Speed (ns) CY62127DV30L 2.2 3.0 3.6 45 45 CY62127DV30L 2.2 3.0 3.6 55 CY62127DV30LL 2.2 3.0 3.6 55 CY62127DV30L 2.2 3.0 3.6 CY62127DV30LL CY62127DV30LL f = 1 MHz [4] Typ 0.85 Max. Standby ISB2 (µA) f = fMAX Typ. [4] Max. Range Typ.[4] Max. 13 Ind’l 1.5 5 1.5 6.5 0.85 1.5 6.5 13 Ind’l 1.5 4 0.85 1.5 5 10 Ind’l 1.5 5 Auto 1.5 15 0.85 1.5 5 10 Ind’l 1.5 4 70 0.85 1.5 5 10 Ind’l 1.5 5 70 0.85 1.5 5 10 Ind’l 1.5 4 Pin Configurations[2, 3] FBGA (Top View) 4 5 3 6 A1 A2 NC A4 CE I/O0 1 2 BLE OE A0 I/O8 BHE A3 TSOP II (Forward) Top View A B C I/O9 I/O10 A5 A6 I/O1 I/O2 VSS I/O11 NC A7 I/O3 VCC D I/O4 VSS E VCC I/O12 DNU NC I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 DNU Notes: 2. NC pins are not connected to the die. 3. Pin #23 of TSOP II and E3 ball of FBGA are DNU, which have to be left floating or tied to Vss to ensure proper application. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M). 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05229 Rev. *H Page 2 of 11 CY62127DV30 DC Input Voltage[5] ................................ −0.3V to VCC + 0.3V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................. –65°C to +150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential ......................................................................... −0.3V to 3.9V Range DC Voltage Applied to Outputs in High-Z State[5] ....................................−0.3V to VCC + 0.3V Ambient Temperature (TA) VCC[6] Industrial –40°C to +85°C 2.2V to 3.6V Automotive –40°C to +125°C 2.2V to 3.6V DC Electrical Characteristics (Over the Operating Range) –45 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description –55 –70 Min. Typ.[4] Max. Min. Typ.[4] Max. Min Typ.[4] Max. Unit Test Conditions Output HIGH Voltage 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0 2.0 2.0 2.7 < VCC < 3.6 IOH = −1.0 mA 2.4 2.4 2.4 Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA 0.4 0.4 0.4 Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC 1.8 + 0.3 VCC 1.8 + 0.3 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC 2.2 + 0.3 VCC 2.2 + 0.3 VCC + 0.3 2.2 < VCC < 2.7 −0.3 0.6 −0.3 0.6 −0.3 0.6 2.7 < VCC < 3.6 −0.3 0.8 −0.3 0.8 −0.3 0.8 −1 +1 −1 +1 −4 +4 −1 +1 −4 +4 Input LOW Voltage Input Leakage GND < VI < VCC Current Output Leakage Current Ind’l Auto GND < VO < VCC, Output Ind’l Disabled Auto VCC Operating f = fMAX = 1/tRC VCC = 3.6V, Supply Current IOUT = 0 mA, f = 1 MHz CMOS level −1 +1 V −1 +1 −1 +1 6.5 13 5 10 5 10 0.85 1.5 0.85 1.5 0.85 1.5 5 1.5 5 1.5 5 1.5 15 1.5 1.5 4 1.5 4 1.5 4 Automatic CE Power-down Current— CMOS Inputs CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V 1.5 5 1.5 5 1.5 5 1.5 15 1.5 4 1.5 4 1.5 4 Auto V µA µA µA CE > VCC − 0.2V, L Ind’l VIN > VCC − 0.2V, VIN Auto < 0.2V, f = fMAX (Address and LL Data Only), f = 0 (OE, WE, BHE and BLE) LL V µA Automatic CE Power-down Current— CMOS Inputs L Ind’l V mA µA µA Capacitance[7] Parameter Description Test Conditions Max. Unit CIN Input Capacitance pF Output Capacitance TA = 25°C, f = 1 MHz VCC = VCC(typ) 8 COUT 8 pF Notes: 5. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.75V for pulse durations less than 20 ns. 6. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µs. 7. Tested initially and after any design or proces changes that may affect these parameters. Document #: 38-05229 Rev. *H Page 3 of 11 CY62127DV30 Thermal Resistance[7] Parameter Description θJA Thermal Resistance (Junction to Ambient) θJC Thermal Resistance (Junction to Case) Test Conditions FBGA TSOP II Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 76 °C/W 12 11 °C/W AC Test Loads and Waveforms[8] R1 VCC OUTPUT ALL INPUT PULSES 90% 90% 10% VCC 10% GND Rise Time = 1 V/ns R2 50 pF INCLUDING JIG AND SCOPE Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5V (2.2V - 2.7V) 3.0V (2.7V - 3.6V) Unit R1 16600 1103 Ω R2 15400 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Conditions VCC=1.5V, CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V VCC VCC Unit V µA L Ind’l 4 L Auto 10 LL Ind’l 3 Operation Recovery Time Data Retention Waveform Max. 1.5 Chip Deselect to Data Retention Time tR[9] Typ.[4] Min. 0 ns 200 µs [10] VV CC(min.) CC(min.) tCDR tCDR DATA MODE DATA RETENTION RETENTION MODE V > 1.5V DR VDR > 1.5V VVCC(min.) CC(min.) tRtR CE oror CE . . BHE BLE BHEBLE Notes: 8. Test condition for the 45-ns part is a load capacitance of 30 pF. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 200 µs. 10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both. Document #: 38-05229 Rev. *H Page 4 of 11 CY62127DV30 Switching Characteristics (Over the Operating Range)[11] CY62127DV30-45 [8] Parameter Description Min. Max. CY62127DV30-55 Min. Max. CY62127DV30-70 Min. Max. Unit Read Cycle tRC Read Cycle Time 45 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 70 ns tDOE OE LOW to Data Valid 25 25 35 ns 25 ns 45 [12] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[12,14] tLZCE CE LOW to Low Z[12] 10 55 10 5 10 70 10 ns 10 ns tHZCE CE HIGH to High tPU CE LOW to Power-up tPD CE HIGH to Power-down 45 55 70 ns tDBE BLE/BHE LOW to Data Valid 45 55 70 ns tLZBE[13] tHZBE BLE/BHE LOW to Low BLE/BHE HIGH to 0 Z[12] 0 5 High-Z[12,14] 20 ns ns 5 20 20 ns 10 5 15 Z[12,14] 70 0 5 15 25 ns 5 20 ns ns 25 ns Write Cycle[15] tWC Write Cycle Time 45 55 70 ns tSCE CE LOW to Write End 40 40 60 ns tAW Address Set-up to Write End 40 40 60 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 35 40 50 ns tBW BLE/BHE LOW to Write End 40 40 60 ns tSD Data Set-up to Write End 25 25 30 ns tHD Data Hold from Write End 0 0 0 ns tHZWE tLZWE WE LOW to High Z[12,14] [12] WE HIGH to Low Z 15 10 20 10 25 5 ns ns Notes: 11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. If both byte enables are toggled together, this value is 10 ns. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05229 Rev. *H Page 5 of 11 CY62127DV30 Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[16,17] tRC ADDRESS tAA tOHA DATA OUT DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled)[16,17,18] Write Cycle No. 1 (WE Controlled)[14, 15, 19, 20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID DON'T CARE tHZOE Notes: 16. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 17. WE is HIGH for Read cycle. 18. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 19. Data I/O is high-impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05229 Rev. *H Page 6 of 11 CY62127DV30 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[14, 15, 19, 20, 21] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE / BLE OE tSD DATA I/O tHD DATA IN VALID DON'T CARE tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[20, 21] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA I/O DATAIN VALID DON'T CARE tHZWE Document #: 38-05229 Rev. *H tHD tLZWE Page 7 of 11 CY62127DV30 Switching Waveforms (continued) Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[20, 21] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O DON'T CARE tHD DATAIN VALID Truth Table CE WE OE BHE BLE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X High Z High Z Deselect/Power-down Standby (I SB ) X X X H H High Z High Z Deselect/Power-down Standby (I SB ) Data Out Data Out Read All bits Active (I CC ) Active (I CC ) L H L L L L H L H L Data Out High Z Read Lower Byte Only L H L L H High Z Data Out Read Upper Byte Only Active (I CC ) L H H L L High Z High Z Output Disabled Active (I CC ) L H H H L High Z High Z Output Disabled Active (I CC ) L H H L H High Z High Z Output Disabled Active (I CC ) L L X L L Data In Data In Write Active (I CC ) L L X H L Data In High Z Write Lower Byte Only Active (I CC ) L L X L H High Z Data In Write Upper Byte Only Active (I CC ) Document #: 38-05229 Rev. *H Page 8 of 11 CY62127DV30 Ordering Information Speed (ns) Ordering Code 45 55 70 Package Diagram Operating Range Package Type CY62127DV30LL-45BVXI 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free) CY62127DV30LL-45ZXI 51-85087 44-lead TSOP Type II (Pb-Free) CY62127DV30LL-55BVI 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62127DV30LL-55BVXI 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free) CY62127DV30LL-55ZI 51-85087 44-lead TSOP Type II CY62127DV30L-55ZXI 51-85087 44-lead TSOP Type II (Pb-Free) CY62127DV30LL-55ZXI 51-85087 44-lead TSOP Type II (Pb-Free) CY62127DV30L-55BVXE 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free) CY62127DV30L-55ZSXE 51-85087 44-lead TSOP Type II (Pb-Free) CY62127DV30L-70BVI 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial Industrial Automotive Industrial CY62127DV30LL-70BVXI 51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free) CY62127DV30L-70ZI 51-85087 44-lead TSOP Type II CY62127DV30LL-70ZXI 51-85087 44-lead TSOP Type II (Pb-Free) Please contact your local Cypress sales representative for availability of these parts Package Diagrams 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 4 5 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.10 C 0.21±0.05 0.25 C B 0.15(4X) 51-85150-*D C Document #: 38-05229 Rev. *H 1.00 MAX 0.26 MAX. SEATING PLANE Page 9 of 11 CY62127DV30 Package Diagrams (continued) 44-lead TSOP II (51-85087) 51-85087-*A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05229 Rev. *H Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62127DV30 Document History Page Document Title: CY62127DV30 MoBL® 1-Mb (64K x 16) Static RAM Document Number: 38-05229 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117690 08/27/02 JUI *A 127311 06/13/03 MPR Changed From Advanced Status to Preliminary Changed Isb2 to 5 µA (L), 4 µA (LL) Changed Iccdr to 4 µA (L), 3 µA (LL) Changed Cin from 6 pF to 8 pF *B 128341 07/22/03 JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information *C 129000 08/29/03 CDY Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA *D 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote # 8 on page #4 Added Lead-Free Package ordering information on page# 9 Changed 44-lead TSOP-II package name from Z44 to ZS44 *E 346982 See ECN AJU Added 56-pin QFN package *F 369955 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Specs for IIX,IOZ,ISB1and ISB2 in the Product portfolio on Page #2 and the DC Electrical Characteristics table on Page# 4 Added Automotive spec for ICCDR in the Data Retention Characteristics table on Page# 5 Added Pb-Free Automotive parts for 55 ns Speed bin *G 457685 See ECN NXR Removed 56-pin QFN package from product offering Updated ordering Information Table *H 470383 See ECN NXR Changed pin #23 of TSOP II from NC to DNU and updated footnote #2 Document #: 38-05229 Rev. *H New Data Sheet Page 11 of 11