CY62128E MoBL®
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99 percent
when deselected (CE1 HIGH or CE2 LOW). The eight input and
output pins (I/O0 through I/O7) are placed in a high impedance
state when the device is deselected (CE1 HIGH or CE2 LOW),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE1 LOW and CE2 HIGH and WE LOW).
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■
Voltage range: 4.5 V to 5.5 V
■
Pin compatible with CY62128B
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A (Industrial)
■
Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin thin small outline package (TSOP) Type I packages
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A16).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The CY62128E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 5 for more details and suggested alternatives.
For a complete list of related resources, click here.
Logic Block Diagram
0
I/O
I/O1
SENSE AMPS
ROW DECODER
1
128K x 8
ARRAY
I/O
I/O22
I/O
I/O33
I/O4
I/O
I/O5
I/O
I/O 6
I/O
6
•
POWER
DOWN
I/O 7
I/O
7
A16
A14
A12
OE
A15
COLUMN DECODER
WE
Cypress Semiconductor Corporation
Document Number: 38-05485 Rev. *P
I/O
I/O0
INPUT BUFFER
A13
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2017
CY62128E MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Document Number: 38-05485 Rev. *P
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
CY62128E MoBL®
Pin Configuration
4
A3
A2
A1
A0
/O0
/O1
O2
VSS
8
9
10
11
12
13
14
15
16
25
24
23
22
21
20
19
18
17
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Figure 1. 32-pin STSOP pinout [1]
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
STSOP
Top View
(not to scale)
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Figure 2. 32-pin TSOP I pinout [1]
32-Pin SOIC
Top View
C
1
16
14
12
A7
A6
A5
2
3
4
A
5
6
7
32
31
30
29
28
27
26
VCC
A15
CE2
WE
A13
A8
A9
A
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP I
Top View
(not to scale)
Figure 3. 32-pin SOIC pinout [1]
Top View
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
26
27
26
28
29
30
31
32
1
2
3
TSOP I
Top View
(not to scale)
STSOP
Top View
(not to scale)
Note
1. NC pins are not connected on the die.
Document Number: 38-05485 Rev. *P
Page 3 of 20
CY62128E MoBL®
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
Min
Typ [2]
Speed
(ns)
Max
CY62128ELL Industrial /
Automotive-A
4.5
5.0
5.5
CY62128ELL Automotive-E
4.5
5.0
5.5
45
[3]
55
Operating ICC (mA)
f = 1MHz
f = fmax
Standby ISB2 (µA)
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
1.3
2
11
16
1
4
1.3
4
11
35
1
30
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
3. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.
Document Number: 38-05485 Rev. *P
Page 4 of 20
CY62128E MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [4, 5] ... –0.5 V to 6.0 V (VCC(max) + 0.5 V)
DC voltage applied to outputs
in High Z State [4, 5] ......... –0.5 V to 6.0 V (VCC(max) + 0.5 V)
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Device
CY62128ELL
Ambient
Temperature
Range
VCC[6]
Industrial / –40 °C to +85 °C 4.5 V to 5.5 V
Automotive-A
Automotive-E –40 °C to +125 °C
DC input voltage[4, 5] ........ –0.5 V to 6.0 V (VCC(max) + 0.5 V)
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
VCC = 4.5 V
VCC = 5.5 V
IOH = –1 mA
Min Typ [7]
2.4
–
Max
–
Min Typ [7]
2.4
[8]
–
Unit
Max
–
–
–
–
–
0.4
–
–
0.4
V
VCC = 4.5 V to 5.5 V
2.2
–
VCC + 0.5
2.2
–
VCC + 0.5
V
Input LOW voltage
VCC = 4.5 V to 5.5 V
–0.5
–
0.8
–0.5
–
0.8
V
GND < VI < VCC
IOL = 2.1 mA
VIH
Input HIGH voltage
VIL
3.4
V
[8]
–
Output LOW voltage
3.4
55 ns (Automotive-E)
–
VOL
IOH = –0.1 mA
45 ns (Industrial/
Automotive-A)
IIX
Input leakage current
–1
–
+1
–4
–
+4
A
IOZ
Output leakage current GND < VO < VCC, Output Disabled
–1
–
+1
–4
–
+4
A
ICC
VCC Operating supply
current
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–
11
16
–
11
35
mA
–
1.3
2
–
1.3
4
Automatic CE
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
power-down
VIN > VCC – 0.2 V or VIN < 0.2 V,
Current—CMOS inputs f = 0, VCC = VCC(max)
–
1
4
–
1
30
ISB2 [9]
f = fmax = 1/tRC
f = 1 MHz
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
9. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05485 Rev. *P
Page 5 of 20
CY62128E MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [10]
Test Conditions
32-pin SOIC
Package
32-pin STSOP
Package
32-pin TSOP
Package
Unit
Still Air, soldered on a 3 × 4.5
inch, two-layer printed circuit
board
48.67
32.56
33.01
C/W
25.86
3.59
3.42
C/W
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
3.0 V
30 pF
R2
INCLUDING
JIG AND
SCOPE
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
90%
10%
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
OUTPUT
RTH
Parameters
Value
Unit
R1
1800
R2
990
RTH
639
VTH
1.77
V
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05485 Rev. *P
Page 6 of 20
CY62128E MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Min
Typ [11]
Max
Unit
2
–
–
V
Industrial /
Automotive-A
–
–
4
Automotive-E
–
–
30
0
–
–
ns
CY62128ELL-45
45
–
–
ns
CY62128ELL-55
55
–
–
Conditions
VCC for data retention
[12]
Data retention current
VCC = VDR,
CE1 > VCC 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR [13]
Chip deselect to data
retention time
tR [14]
Operation recovery time
A
A
Data Retention Waveform
Figure 5. Data Retention Waveform [15]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2.0 V
VCC(min)
tR
CE
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
15. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document Number: 38-05485 Rev. *P
Page 7 of 20
CY62128E MoBL®
Switching Characteristics
Over the Operating Range
Parameter [16]
Description
45 ns (Industrial /
Automotive-A)
Min
55 ns (Automotive-E)
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
tLZOE
OE LOW to Low Z[17]
5
–
5
–
ns
tHZOE
tLZCE
OE HIGH to High
Z[17, 18]
–
18
–
20
ns
Z[17]
10
–
10
–
ns
Z[17, 18]
CE1 LOW and CE2 HIGH to Low
tHZCE
CE1 HIGH or CE2 LOW to High
–
18
–
20
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
CE1 HIGH or CE2 LOW to power-down
–
45
–
55
ns
tPD
Write Cycle
[19, 20]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to High Z
WE HIGH to Low
[17, 18]
Z[17]
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 4 on page 6.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
18. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
20. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 38-05485 Rev. *P
Page 8 of 20
CY62128E MoBL®
Switching Waveforms
Figure 6. Read Cycle 1 (Address Transition Controlled) [21, 22]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23, 24]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
tLZCE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document Number: 38-05485 Rev. *P
Page 9 of 20
CY62128E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled) [25, 26, 27, 28]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 29
tHD
DATA VALID
tHZOE
Notes
25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
26. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
29. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05485 Rev. *P
Page 10 of 20
CY62128E MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [30, 31, 32, 33]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [30, 33, 34]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 35
tHD
DATA VALID
tHZWE
tLZWE
Notes
30. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
31. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
32. Data I/O is high impedance if OE = VIH.
33. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
34. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
35. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05485 Rev. *P
Page 11 of 20
CY62128E MoBL®
Truth Table
CE1
WE
OE
[36]
X
X
High Z
Deselect/Power down
Standby (ISB)
[36]
L
X
X
High Z
Deselect/Power down
Standby (ISB)
L
H
H
L
Data Out
Read
Active (ICC)
L
H
L
X
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, outputs disabled
Active (ICC)
H
X
CE2
X
Inputs/Outputs
Mode
Power
Note
36. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05485 Rev. *P
Page 12 of 20
CY62128E MoBL®
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62128ELL-45SXI
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-45ZAXI
51-85094 32-pin STSOP (Pb-free)
CY62128ELL-45ZXI
51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-45SXA
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-45ZXA
51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-55SXE
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-55ZAXE
51-85094 32-pin STSOP (Pb-free)
Operating
Range
Industrial
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 2
8
E
LL - XX XX X
X
Temperature Grade: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = S or ZA or Z
S = 32-pin SOIC
ZA = 32-pin STSOP
Z = 32-pin TSOP Type I
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
Process Technology: E = 90 nm Technology
Bus width = × 8
Density = 1-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05485 Rev. *P
Page 13 of 20
CY62128E MoBL®
Package Diagrams
Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45 Package Outline, 51-85081
51-85081 *E
Document Number: 38-05485 Rev. *P
Page 14 of 20
CY62128E MoBL®
Package Diagrams (continued)
Figure 12. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32 Package Outline, 51-85094
51-85094 *G
Document Number: 38-05485 Rev. *P
Page 15 of 20
CY62128E MoBL®
Package Diagrams (continued)
Figure 13. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32R Package Outline, 51-85056
51-85056 *G
Document Number: 38-05485 Rev. *P
Page 16 of 20
CY62128E MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
SRAM
Static Random Access Memory
s
microsecond
SOIC
Small Outline Integrated Circuit
mA
milliampere
STSOP
Small Thin Small Outline Package
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
WE
Write Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05485 Rev. *P
Symbol
Unit of Measure
Page 17 of 20
CY62128E MoBL®
Document History Page
Document Title: CY62128E MoBL®, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05485
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
203120
See ECN
AJU
New data sheet
*A
299472
See ECN
SYT
Converted from Advance Information to Preliminary
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
Changed tDOE from 15 ns to 18 ns for 35 ns speed bin
Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed
bins, respectively
Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed
bins, respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed
bins, respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of ISB1, ISB2 and ICCDR from 1.0 A to 1.5 A
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for
f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Removed ISB1 DC Specs from Electrical characteristics table
Changed ISB2 (max) from 1.5 A to 4 A
Changed ISB2 (Typ) from 0.5 A to 1 A
Changed ICCDR (max) from 1.5 A to 4 A
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information Table
Description of Change
*C
464721
See ECN
NXR
Updated the Block Diagram on page # 1
*D
563144
See ECN
AJU
Added footnote 4 on page 2
*E
1024520
See ECN
VKN
Added Automotive-A information
Converted Automotive-E specs to final
Added footnote #9 related to ISB2 and ICCDR
Updated Ordering Information table
*F
2548575
08/05/08
NXR
Corrected typo error in Ordering Information table
*G
2934396
06/03/10
VKN
Added footnote #22 related to chip enable
Updated package diagrams
Updated template
*H
3113780
12/17/2010
PRAS
Document Number: 38-05485 Rev. *P
Updated Logic Block Diagram.
Added Ordering Code Definitions.
Page 18 of 20
CY62128E MoBL®
Document History Page (continued)
Document Title: CY62128E MoBL®, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05485
Rev.
ECN No.
Submission
Date
Orig. of
Change
*I
3223635
04/12/2011
RAME
Removed V30 value from Ordering Code Definition.
Updated Package diagram 51-85056 from *E to *F and 51-85094 *E to *F
Added Acronyms and Units of Measure.
Updated to new template.
*J
3292276
06/24/2011
RAME
Updated Data Retention Characteristics (Changed the conditions and
minimum value of tR parameter).
Updated to new template.
*K
4018425
06/03/2013
MEMJ
Updated Functional Description.
Description of Change
Updated Electrical Characteristics:
Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH
parameter and added maximum value corresponding to that Test Condition.
Added Note 8 and referred the same note in maximum value for VOH
parameter corresponding to Test Condition “VCC = 5.5 V, IOH = –0.1 mA”.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *C to *E.
Completing Sunset Review.
*L
4410948
06/17/2014
VINI
Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 34 and referred the same note in Figure 10.
Updated Package Diagrams:
spec 51-85094 – Changed revision from *F to *G.
spec 51-85056 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*M
4478332
08/19/2014
BMAH
Updated Truth Table:
Fixed typo (Replaced WE with WE and OE with OE in the header row).
*N
4581542
11/27/2014
VINI
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
*O
4797476
06/15/2015
*P
5726469
05/04/2017
Document Number: 38-05485 Rev. *P
VINI
Updated to new template.
Completing Sunset Review.
AESATMP7 Updated Cypress Logo and Copyright.
Page 19 of 20
CY62128E MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05485 Rev. *P
Revised May 4, 2017
Page 20 of 20
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