CY62128EV30LL-45ZXAT

CY62128EV30 MoBL® Automotive 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Very high-speed: 45 ns ■ Temperature ranges: ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62128DV30 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 4 A ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 32-pin small outline integrated circuit (SOIC), 32-pin thin small outline package (TSOP) Type I, and 32-pin STSOP packages To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 through A16). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Logic Block Diagram SENSE AMPS ROW DECODER I/O 1 128K x 8 ARRAY I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 • POWER DOWN I/O 7 A16 A14 A12 OE A15 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 001-65528 Rev. *B I/O 0 INPUT BUFFER A13 CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 6, 2012 CY62128EV30 MoBL® Automotive Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Document #: 001-65528 Rev. *B Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 2 of 18 CY62128EV30 MoBL® Automotive Pin Configuration Figure 1. 32-pin STSOP [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 Figure 2. 32-pin TSOP I [1] 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Top View (not to scale) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Top View (not to scale) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Figure 3. 32-pin SOIC [1] Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz Min Typ [2] Max Standby ISB2 (µA) f = fmax Typ [2] Max Typ [2] Max Typ [2] Max CY62128EV30LL Automotive-A 2.2 3.0 3.6 45 1.3 2.0 11 16 1 4 CY62128EV30LL Automotive-E 2.2 3.0 3.6 55 1.3 4.0 11 35 1 30 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 001-65528 Rev. *B Page 3 of 18 CY62128EV30 MoBL® Automotive Pin Definitions I/O Type Description Input A0–A16. Address inputs Input/output I/O0–I/O7. Data lines. Used as input or output lines depending on operation. Input/control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/control CE1. Chip Enable 1, Active LOW. Input/control CE2. Chip Enable 2, Active HIGH. Input/control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When de-asserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground GND. Ground for the device. Power supply VCC. Power supply for the device. Document #: 001-65528 Rev. *B Page 4 of 18 CY62128EV30 MoBL® Automotive Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Static discharge voltage ......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up current ..................................................... > 200 mA Operating Range Supply voltage to ground potential .......................................–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High Z state [3, 4] ......................–0.3 V to VCC(max) + 0.3 V Device Ambient Temperature Range VCC[5] CY62128EV30LL Automotive-A –40 °C to +85 °C 2.2 V to Automotive-E –40 °C to +125 °C 3.6 V DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH voltage Test Conditions 45 ns (Auto-A) Min Typ [6] Max 55 ns (Auto-E) Min Typ [6] Max Unit IOH = –0.1 mA, VCC < 2.70 V 2.0 – – 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – 2.4 – – V – – 0.4 – – 0.4 V VOL Output LOW voltage IOL = 0.1 mA – – 0.4 – – 0.4 V VIH Input HIGH voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V 1.8 – VCC + 0.3 V V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 V 2.2 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V VCC = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V –1 – +1 –4 – +4 A IOL = 2.1 mA, VCC > 2.70 V VIL Input LOW voltage IIX Input leakage current GND < VIN < VCC IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 –4 – +4 A ICC VCC operating supply current – 11 16 – 11 35 mA – 1.3 2.0 – 1.3 4.0 mA f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA f = 1 MHz CMOS levels ISB1[7] CE1 > VCC0.2 V, CE2 < 0.2 V, Automatic CE power-down VIN > VCC – 0.2 V, VIN < 0.2 V, current — CMOS inputs f = fmax (address and data only), f = 0 (OE and WE), VCC = 3.60 V – 1 4 – 1 35 A ISB2[7] Automatic CE CE1 > VCC – 0.2 V, CE2 < 0.2 V, power-down VIN > VCC – 0.2 V or VIN < 0.2 V, current — CMOS inputs f = 0, VCC = 3.60 V – 1 4 – 1 30 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-65528 Rev. *B Page 5 of 18 CY62128EV30 MoBL® Automotive Capacitance Parameter [8] CIN Description Test Conditions Input capacitance COUT TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Output capacitance Max Unit 10 pF 10 pF Thermal Resistance Parameter [8] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions 32-pin TSOP I 32-pin SOIC 32-pin STSOP Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 °C/W 3.42 25.86 3.59 °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms R1 All Input Pulses VCC output VCC 30 pF including JIG and scope 90% 10% R2 GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH Output V Parameters 2.50 V 3.0 V Unit R1 16667 1103  R2 15385 1554  RTH 8000 645  VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-65528 Rev. *B Page 6 of 18 CY62128EV30 MoBL® Automotive Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR[10] Data retention current tCDR[11] Chip deselect to data retention time tR[12] Operation recovery time Min Typ [9] Max Unit 1.5 – – V Automotive-A – – 3 A Automotive-E – – 30 A 0 – – ns CY62128EV30LL-45 45 – – ns CY62128EV30LL-55 55 – – Conditions VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 5. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min)  100 s. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 001-65528 Rev. *B Page 7 of 18 CY62128EV30 MoBL® Automotive Switching Characteristics Over the Operating Range Parameter [14, 15] Description 45 ns (Automotive-A) 55 ns (Automotive-E) Min Max Min Max Unit Read Cycle tRC Read cycle time 45 – 55 – ns tAA Address to data valid – 45 – 55 ns tOHA Data hold from address change 10 – 10 – ns tACE CE LOW to data valid – 45 – 55 ns tDOE OE LOW to data valid – 22 – 25 ns [16] 5 – 5 – ns – 18 – 20 ns 10 – 10 – ns – 18 – 20 ns tLZOE tHZOE tLZCE OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z [16, 17] [16] [16, 17] tHZCE CE HIGH to High Z tPU CE LOW to Power-up 0 – 0 – ns tPD CE HIGH to Power-down – 45 – 55 ns tWC Write cycle time 45 – 55 – ns tSCE CE LOW to write end 35 – 40 – ns tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data Hold from write end 0 – 0 – ns – 18 – 20 ns 10 – 10 – ns Write Cycle [18] tHZWE tLZWE WE LOW to High Z [16, 17] WE HIGH to Low Z [16] Notes 14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 4 on page 6. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-65528 Rev. *B Page 8 of 18 CY62128EV30 MoBL® Automotive Switching Waveforms Figure 6. Read Cycle 1 (Address Transition Controlled) [20, 21] tRC RC Address tAA tOHA DATA I/O Previous Data Valid DATAOUTVALID Figure 7. Read Cycle No. 2 (OE Controlled) [21, 22, 23] Address tRC CE tACE OE tHZOE tDOE tHZCE tLZOE High Impedance DATAOUTVALID DATA I/O tLZCE tPD tPU VCC Supply Current High Impedance ICC 50% 50% ISB Figure 8. Write Cycle No. 1 (WE Controlled) [19, 22, 24, 25] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O NOTE 26 tHD DATAINVALID tHZOE Notes 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 21. WE is HIGH for read cycle. 22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 23. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 24. Data I/O is high impedance if OE = VIH. 25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 26. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-65528 Rev. *B Page 9 of 18 CY62128EV30 MoBL® Automotive Switching Waveforms (continued) Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [27, 28, 29, 30] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATAINVALID Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 30] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 31 tHD DATAINVALID tHZWE tLZWE Notes 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH 28. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 29. Data I/O is high impedance if OE = VIH. 30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 31. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-65528 Rev. *B Page 10 of 18 CY62128EV30 MoBL® Automotive Truth Table CE1 WE OE Inputs/Outputs Mode Power [32] X X High Z Deselect/Power-down Standby (ISB) [32] L X X High Z Deselect/Power-down Standby (ISB) L H H L Data out Read Active (ICC) L H L X Data in Write Active (ICC) L H H H High Z Selected, outputs disabled Active (ICC) H X CE2 X Note 32. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-65528 Rev. *B Page 11 of 18 CY62128EV30 MoBL® Automotive Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram Package Type CY62128EV30LL-45SXA 51-85081 32-pin 450-Mil SOIC (Pb-free) CY62128EV30LL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free) CY62128EV30LL-45ZAXA 51-85094 32-pin STSOP (Pb-free) CY62128EV30LL-55ZXE 51-85056 32-pin TSOP Type I (Pb-free) CY62128EV30LL-55SXE 51-85081 32-pin 450-Mil SOIC (Pb-free) Operating Range Automotive-A Automotive-E Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 2 8 E V30 LL - XX XX X X Temperature Grade: X = A or E A = Automotive-A; E = Automotive-E Pb-free Package Type: XX = S or Z or ZA S = 32-pin SOIC Z = 32-pin TSOP Type I ZA = 32-pin STSOP Speed Grade: XX = 45 ns or 55 ns LL = Low Power Voltage Range: 3 V Typical E = Process Technology 90 nm Bus width = × 8 Density = 1-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 001-65528 Rev. *B Page 12 of 18 CY62128EV30 MoBL® Automotive Package Diagrams Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 51-85081 *D Document #: 001-65528 Rev. *B Page 13 of 18 CY62128EV30 MoBL® Automotive Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056 51-85056 *F Document #: 001-65528 Rev. *B Page 14 of 18 CY62128EV30 MoBL® Automotive Package Diagrams (continued) Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 51-85094 *F Document #: 001-65528 Rev. *B Page 15 of 18 CY62128EV30 MoBL® Automotive Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius I/O input/output MHz megahertz OE output enable A microamperes SOIC small outline integrated circuit s microseconds SRAM static random access memory mA milliamperes STSOP small thin small outline package ns nanoseconds TSOP thin small outline package  ohms WE write enable % percent pF picofarad V Volts W Watts Document #: 001-65528 Rev. *B Symbol Unit of Measure Page 16 of 18 CY62128EV30 MoBL® Automotive Document History Page Document Title: CY62128EV30 MoBL® Automotive, 1-Mbit (128 K × 8) Static RAM Document Number: 001-65528 Rev. ECN No. Submission Orig. of Date Change ** 3115909 01/06/2011 RAME New Datasheet for Automotive SRAM parts. Created separate datasheet for Automotive SRAM parts from Document no. 38-05579 Rev. *H *A 3288690 06/21/2011 RAME Removed the Note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.” and its reference in Functional Description. Updated Electrical Characteristics (Test Conditions of ISB1 and ISB2 parameters). Updated Package Diagrams. Updated in new template. *B 3543173 03/06/2012 TAVA Updated Electrical Characteristics Table Updated Switching Waveforms Updated Package Diagrams Document #: 001-65528 Rev. *B Description of Change Page 17 of 18 CY62128EV30 MoBL® Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-65528 Rev. *B Revised March 6, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18