CY62128VLL-70SI

1*CY62128V Family CY62128V Family 128K x 8 Static RAM Features • Low voltage range: — 2.7V–3.6V (CY62128V) — 2.3V–2.7V (CY62128V25) • • • • • — 1.6V–2.0V (CY62128V18) Low active power and standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power LOW Output Enable (OE) and three-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. The CY62128V family is available in the standard 450-mil-wide SOIC, 32-lead TSOP-I, and STSOP packages. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Functional Description The CY62128V family is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active Logic Block Diagram Pin Configurations Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 INPUT BUFFER I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 512x 256x 8 ARRAY 62128V-2 CE 1 CE 2 WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A9 A 10 A 11 A12 A13 A14 A15 A16 62128V-1 A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reverse TSOP I Top View (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 STSOP Top View (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 62128V-3 62128V-4 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 27, 2001 CY62128V Family Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] .................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 1.6V to 3.6V 1.6V to 3.6V Product Portfolio Power Dissipation (Commercial) VCC Range Product CY62128V CY62128V25 CY62128V18 Min. 2.7V 2.3V 1.6V Typ. [2] Operating (ICC) Max. 3.6V 2.7V 2.0V Speed 55, 70 ns 100 ns 200 ns Typ. [2] Standby (ISB2) Typ. [2] Maximum 40 mA 20 mA 15 mA Maximum 100 µA (XL = 10 µA) 50 µA (LL = 12 µA) 30 µA (LL = 10 µA) 3.0V 2.5V 1.8V 20 mA 15 mA 10 mA 0.4 µA 0.3 µA 0.3 µA Electrical Characteristics Over the Operating Range CY62128V-55/70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com’l, 70 ns Ind’l, 55 ns Ind’l, 70 ns ISB1 Automatic CE Power-Down Current— TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Com’l, 70 ns Coml, 55 ns Ind’l L LL, XL LL L LL L LL, XL LL L LL Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA 2 –0.5 –1 –1 ±1 ±1 20 20 23 20 20 15 15 17 15 15 Min. 2.4 0.4 VCC +0.5V 0.8 +1 +1 40 40 50 40 40 300 300 350 300 300 µA Typ.[2] Max. Unit V V V V µA µA mA Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C. 2 CY62128V Family Electrical Characteristics Over the Operating Range (continued) CY62128V-55/70 Parameter ISB2 Description Automatic CE Power-Down Current— CMOS Inputs Test Conditions Max. VCC, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Com’l L LL XL Ind’l L LL Min. Typ.[2] 0.4 Max. 100 15 10 100 30 Unit µA µA µA µA µA Electrical Characteristics Over the Operating Range CY62128V25-100 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Indust’l Temp Range L LL L LL L LL LL 0.4 50 12 24 0.4 30 10 20 µA µA µA 15 300 5 100 µA Test Conditions VCC = Min., IOH = –0.1 mA VCC = Min., IOL = 0.1 mA 2 –0.5 –1 –1 ±1 ±1 15 Min. 2.4 0.4 VCC +0.5 0.8 +1 +1 20 0.7* VCC –0.5 –1 –1 ±0.1 ±0.1 10 Typ. [2] CY62128V18-200 Min. 0.8* VCC 0.2 VCC +0.3 0.3* VCC +1 +1 15 Typ.[2] Max. Unit V V V V µA µA mA Max. ISB1 ISB2 Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 CY62128V Family AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 1.8V 10% GND < 5 ns 62128V–5 ALL INPUT PULSES 90% 90% 10% < 5 ns 62128V–6 Equivalent to: THÉVENIN EQUIVALENT RTH V OUTPUT Parameters R1 R2 RTH VTH 3.3V 1213 1378 645 1.75V 2.5V 15909 4487 3500 0.55V 1.8V 10800 4154 3000 0.50V Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Com’l L LL, XL Ind’l tCDR[3] tR L LL Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V No input may exceed VCC+0.3V 0 tRC Conditions[4] Min. 1.6 0.4 10 10 20 20 Typ.[2] Max. Unit V µA µA µA µA ns ns Data Retention Waveform DATA RETENTION MODE VCC 1.8V tCDR CE C62128V–7 VDR > 1.6 V 1.8V tR Note: 4. No input may exceed VCC+0.3V. 4 CY62128V Family Data Retention Current Graph (for “L” version only) DATA RETENTIO N CURRENT vs. SUPPLY VOLTAGE 80 SUPPLY CURRENT (µA) 70 60 50 40 30 20 10 0 2.6 1.6 3.6 TA =25°C SUPPLY VOLTAGE (V) Switching Characteristics Over the Operating Range[5] 62128V-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE 5. 6. 7. 8. 9. 62128V-70 Min. 70 Max. 62128V25-100 Min. 100 Max. 62128V18-200 Min. 200 Max. Unit ns 200 10 200 125 10 75 10 75 0 200 200 190 190 0 0 125 100 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 15 ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[6] Z[6, 7] Z[6] Min. 55 Max. 55 5 55 20 10 20 10 20 0 55 55 45 45 0 0 45 25 0 20 5 5 70 60 60 0 0 55 30 0 0 10 10 10 70 10 70 35 10 25 10 25 0 70 100 100 100 0 0 90 60 0 25 10 100 100 75 50 50 100 OE HIGH to High CE HIGH to High Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down [8, 9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[6, 7] WE HIGH to Low Z[6] 50 Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE signals must be LOW and CE2 HIGH to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY62128V Family Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID 62128V–8 Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB 62128V-9 HIGH IMPEDANCE DATA OUT ICC Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID 62128V-10 tHA tHD Notes: 10. Device is continuously selected. OE, CE = VIL, CE2=VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 6 CY62128V Family Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID 62128V-11 tHD Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0–I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Note: 15. During this period, the I/Os are in output state and input signals should not be applied. 7 CY62128V Family Ordering Information Speed (ns) 55 70 Ordering Code CY62128VLL-55ZAI CY62128VL-70SC CY62128VLL-70SC CY62128VL-70ZC CY62128VLL-70ZC CY62128VL-70ZAC CY62128VLL-70ZAC CY62128VLL-70ZRC CY62128VLL-70SI CY62128VL-70ZI CY62128VLL-70ZI CY62128VL-70ZAI CY62128VLL-70ZAI CY62128VLL-70ZRI 200 CY62128V18L-200ZC CY62128V18L-200ZAI CY62128V18LL-200ZAI Document #: 38-00547-*C ZR32 Z32 ZA32 32-Lead Reverse TSOP Type 1 32-Lead TSOP Type 1 32-Lead STSOP Type 1 Commercial Industrial ZA32 32-Lead STSOP Type 1 ZR32 S34 Z32 32-Lead Reverse TSOP Type 1 32-Lead 450-Mil SOIC 32-Lead TSOP Type 1 Industrial ZA32 32-Lead STSOP Type 1 Z32 32-Lead TSOP Type 1 Package Name ZA32 S34 Package Type 32-Lead STSOP Type 1 32-Lead 450-Mil SOIC Operating Range Industrial Commercial 8 CY62128V Family Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 51-85081-A 9 CY62128V Family Package Diagrams 32-Lead Thin Small Outline Package Z32 51-85056-C 10 CY62128V Family Package Diagrams 32-Lead Shrunk Thin Small Outline Package ZA32 51-85094-C 11 CY62128V Family Package Diagrams 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-B © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.