CY62136FV30LL-45ZSXA

CY62136FV30 MoBL® 2 Mbit (128K x 16) Static RAM Features ■ ■ Very high speed: 45 ns Temperature ranges ❐ Industrial: –40°C to +85°C ❐ Automotive-A: –40°C to +85°C ❐ Automotive-E: –40°C to +125°C ■ Wide voltage range: 2.20V to 3.60V ■ ■ automatic power down feature that significantly reduces power consumption by 90 percent when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ ■ ■ ■ Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Write operation is active (CE LOW and WE LOW) Pin compatible with CY62136V, CY62136CV30/CV33, and CY62136EV30 Ultra low standby power ❐ Typical standby current: 1 μA ❐ Maximum standby current: 5 μA (Industrial) ■ Ultra low active power ❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed) ■ Easy memory expansion with CE and OE features ■ ■ ■ Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 48-ball VFBGA and 44-pin TSOP II packages Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the “Truth Table” on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Functional Description The CY62136FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 128K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 001-08402 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 11, 2009 [+] Feedback CY62136FV30 MoBL® Product Portfolio Power Dissipation Product Range VCC Range (V) Min CY62136FV30LL Industrial/Auto-A Auto-E 2.2 2.2 Typ [1] Speed (ns) Operating ICC (mA) f = 1 MHz Typ [1] f = fmax Typ[1] 13 15 Max 18 25 Standby ISB2 (μA) Typ[1] 1 1 Max 5 20 Max 3.6 3.6 45 55 Max 2.5 3 3.0 3.0 1.6 2 Pin Configuration Figure 1. 48-Ball VFBGA Pinout [2, 3] 1 BLE IO8 IO9 VSS VCC IO14 IO15 NC 2 OE BHE IO10 IO11 IO12 IO13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO1 IO3 IO4 IO5 WE A11 6 NC IO0 IO2 VCC VSS IO6 IO7 NC A B C D E F G H Figure 2. 44-Pin TSOP II [2] A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively. Document Number: 001-08402 Rev. *F Page 2 of 12 [+] Feedback CY62136FV30 MoBL® Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied .......................................... –55°C to + 125°C Supply Voltage to Ground Potential ............................. –0.3V to 3.9V (VCC(max) + 0.3V) DC Voltage Applied to Outputs in High Z State [4, 5].............. –0.3V to 3.9V (VCC(max) + 0.3V) DC Input Voltage [4, 5] .......... –0.3V to 3.9V (VCC(max) + 0.3V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA Operating Range Device Range Auto-E Ambient Temperature –40°C to +125°C VCC [6] CY62136FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V Electrical Characteristics Over the Operating Range -45 (Industrial/Auto-A) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS Levels IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1mA 1.8 2.2 –0.3 –0.3 –1 –1 13 1.6 1 Min Typ[1] 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 18 2.5 5 1.8 2.2 –0.3 –0.3 –4 –4 15 2 1 Max 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +4 +4 25 3 20 μA -55 (Auto-E) Min Typ[1] Max Unit V V V V V V V V μA μA mA ISB1 CE > VCC – 0.2V, Automatic CE Power Down Current — CMOS VIN > VCC – 0.2V, VIN < 0.2V, Inputs f = fmax (Address and Data Only), f = 0 (OE, WE, BHE, and BLE), VCC = 3.60V CE > VCC – 0.2V, Automatic CE Power Down Current — CMOS VIN > VCC – 0.2V or VIN < 0.2V, Inputs f = 0, VCC = 3.60V ISB2 [7] 1 5 1 20 μA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Input Capacitance CIN Output Capacitance COUT Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max)=VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the ISB2 / ICCDR specification. Other inputs can be left floating. Document Number: 001-08402 Rev. *F Page 3 of 12 [+] Feedback CY62136FV30 MoBL® Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 3. AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 × 4.5 inch, two layer printed circuit board VFBGA 75 10 TSOP II 77 13 Unit °C/W °C/W Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V 2.5V (2.2V to 2.7V) 16667 15385 8000 1.20 3.0V (2.7V to 3.6V) 1103 1554 645 1.75 Unit Ω Ω Ω V Parameters R1 R2 RTH VTH Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR tR [9] [7] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = 1.5V, CE > VCC - 0.2V, Industrial/Auto-A VIN > VCC - 0.2V or VIN < 0.2V Auto-E Min 1.5 Typ [1] Max 4 12 Unit V μA ns ns [8] 0 tRC Figure 4. Data Retention Waveform [10] VCC(min) tCDR DATA RETENTION MODE VDR > 1.5V VCC CE or BHE.BLE VCC(min) tR Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document Number: 001-08402 Rev. *F Page 4 of 12 [+] Feedback CY62136FV30 MoBL® Switching Characteristics Over the Operating Range [11, 12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [13] OE HIGH to High Z [13, 14] CE LOW to Low Z [13] Description -45 (Industrial/Auto-A) Min Max -55 (Auto-E) Min Max Unit 45 45 10 45 22 5 18 10 18 0 45 22 5 18 55 55 10 55 25 5 20 10 20 0 55 25 5 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE HIGH to High Z [13, 14] CE LOW to Power Up CE HIGH to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z [13] BLE/BHE HIGH to High Z [13, 14] Write Cycle [15] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold From Write End WE LOW to High Z [13, 14] WE HIGH to Low Z [13] 45 35 35 0 0 35 35 25 0 18 10 55 40 40 0 0 40 40 25 0 20 10 ns ns ns ns ns ns ns ns ns ns ns Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write. Document Number: 001-08402 Rev. *F Page 5 of 12 [+] Feedback CY62136FV30 MoBL® Switching Waveforms Figure 5. Read Cycle No.1: Address Transition Controlled. [16, 17] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 6. Read Cycle No. 2: OE Controlled [17, 18] ADDRESS tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE Notes 16. The device is continuously selected. OE, CE = VIL, BHE and BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 001-08402 Rev. *F Page 6 of 12 [+] Feedback CY62136FV30 MoBL® Switching Waveforms (continued) Figure 7. Write Cycle No 1: WE Controlled [15, 19, 20] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA BHE/BLE tBW OE DATA I/O NOTE 21 tHZOE tSD DATAIN tHD Figure 8. Write Cycle 2: CE Controlled [15, 19, 20] tWC ADDRESS tSCE CE tSA WE tAW tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 21 tHZOE DATAIN tHD Notes 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals. Document Number: 001-08402 Rev. *F Page 7 of 12 [+] Feedback CY62136FV30 MoBL® Switching Waveforms (continued) Figure 9. Write Cycle 3: WE controlled, OE LOW [20] tWC ADDRESS tSCE CE BHE/BLE tAW WE tSA tBW tHA tPWE tSD DATA I/O NOTE 21 tHZWE DATAIN tHD tLZWE Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [20] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tHZWE tHA tBW tPWE tSD DATAIN tLZWE tHD DATA I/O NOTE 21 Document Number: 001-08402 Rev. *F Page 8 of 12 [+] Feedback CY62136FV30 MoBL® Truth Table CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE BLE X H L H L L H L L H L X H L L H L L H L L H Inputs or Outputs High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Data Out (I/O8–I/O15); I/O0–I/O7 in High Z High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); I/O8–I/O15 in High Z Data In (I/O8–I/O15); I/O0–I/O7 in High Z Mode Deselect or Power Down Deselect or Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document Number: 001-08402 Rev. *F Page 9 of 12 [+] Feedback CY62136FV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62136FV30LL-45BVXI CY62136FV30LL-45ZSXI CY62136FV30LL-45ZSXA 55 CY62136FV30LL-55ZSXE Package Diagram Package Type Operating Range Industrial Automotive-A Automotive-E 51-85150 48-Ball VFBGA (Pb-Free) 51-85087 44-Pin TSOP II (Pb-Free) 51-85087 44-Pin TSOP II (Pb-Free) 51-85087 44-Pin TSOP II (Pb-Free) Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.00±0.10 8.00±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.00±0.10 A 1.875 0.75 3.75 B 6.00±0.10 0.55 MAX. 0.25 C 0.15(4X) 0.21±0.05 0.10 C 1.00 MAX SEATING PLANE 0.26 MAX. C 51-85150-*D Document Number: 001-08402 Rev. *F Page 10 of 12 [+] Feedback CY62136FV30 MoBL® Package Diagrams (continued) Figure 12. 44-Pin TSOP II 51-85087-*A Document Number: 001-08402 Rev. *F Page 11 of 12 [+] Feedback CY62136FV30 MoBL® Document History Page Document Title: CY62136FV30 MoBL® 2 Mbit (128K x 16) Static RAM Document Number: 001-08402 Submission Orig. of Rev. ECN No. Date Change Description of Change ** 467351 See ECN NXR New datasheet *A 797956 See ECN VKN Converted from preliminary to final Changed ISB1(typ) and ISB1(max) specification from 0.5 μA to 1.0 μA and 2.5 μA to 5.0 μA, respectively Changed ISB2(typ) and ISB2(max) specification from 0.5 μA to 1.0 μA and 2.5 μA to 5.0 μA, respectively Changed ICCDR(typ) and ICCDR(max) specification from 0.5 μA to 1.0 μA and 2.5 μA to 4.0 μA, respectively Changed ICC(max) specification from 2.25 μA to 2.5 μA *B 869500 See ECN VKN Added Automotive information Updated Ordering information table Added footnote 12 related to tACE *C 901800 See ECN VKN Added footnote 9 related to ISB2 and ICCDR Made footnote 13 applicable to AC parameters from tACE *D 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final Changed IIX min spec from –1 μA to –4 μA and IIX max spec from +1 μA to +4 μA Changed IOZ min spec from –1 μA to –4 μA and IOZ max spec from +1 μA to +4 μA Changed tDBE spec from 55 ns to 25 ns for automotive part *E 2594937 10/22/08 NXR/PYRS Added Automotive-A information Changed tLZBE from 10 ns to 5 ns for -55. *F 2675375 03/17/2009 VKN/PYRS Corrected typo on page 2 (Corrected ISB2 unit to μA from mA) Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-08402 Rev. *F Revised March 11, 2009 Page 12 of 12 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback