CY62137FV18 MoBL®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
■ ■ ■ ■
Very high speed: 55 ns Wide voltage range: 1.65 V to 2.25 V Pin compatible with CY62137CV18 Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 5 A Ultra low active power ❐ Typical active current: 1.6 mA @ f = 1 MHz Ultra low standby power Easy memory expansion with CE and OE features Automatic power down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Byte power-down feature Available in a Pb-free 48-ball Very fine-pitch ball grid package (VFBGA) package
■
advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), or during an active write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from the memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes.
■ ■ ■ ■ ■ ■
Functional Description
The CY62137FV18 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DATA IN DRIVERS
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0–I/O7 I/O8–I/O15
COLUMN DECODER
BHE WE CE OE BLE
BHE BLE
A14
POWER DOWN CIRCUIT
CE
A11
A12
A13
A15
A16
Cypress Semiconductor Corporation Document #: 001-08030 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised June 17, 2011
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CY62137FV18 MoBL®
Contents
Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16
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Product Portfolio
Power Dissipation Product Min CY62137FV18LL 1.65 VCC Range (V) Typ [1] 1.8 Max 2.25 55 Speed (ns) Operating ICC (mA) f = 1 MHz Typ [1] 1.6 Max 2.5 f = fmax Typ [1] 13 Max 18 Standby ISB2 (A) Typ [1] 1 Max 5
Pin Configuration
Figure 1. 48-ball VFBGA Pinout [2, 3] Top View
1 BLE I/O8 I/O9 2 OE BHE I/O10 3 A0 A3 A5 NC NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
VSS I/O11 VCC I/O12
I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9
Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ....................................................–0.2 V to + 2.45 V DC voltage applied to outputs in High Z State [4, 5] ......................................–0.2 V to 2.45 V DC Input Voltage [4, 5] ..................................–0.2 V to 2.45 V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ........................................ > 2001 V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA
Operating Range
Device CY62137FV18 Range Ambient Temperature VCC [6] Industrial –40 °C to +85 °C 1.65 V to 2.25 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current IOH = –0.1 mA IOL = 0.1 mA VCC = 1.65 V to 2.25 V VCC = 1.65 V to 2.25 V GND < VI < VCC f = fmax = 1/tRC VCC(max) = 2.25 V IOUT = 0 mA CMOS levels VCC(max) = 2.25 V Test Conditions 55 ns Min 1.4 – 1.4 –0.2 –1 –1 – Typ[7] – – – – – – 13 Max – 0.2 VCC + 0.2 V 0.4 +1 +1 18 Unit V V V V A A mA
Output leakage current GND < VO < VCC, output disabled VCC operating supply current
f = 1 MHz ISB1
[8]
– –
1.6 1
2.5 5
mA A
Automatic power-down CE > VCC0.2 V, or VCC(max) = 2.25 V current–CMOS inputs (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, WE) Automatic power-down CE > V – 0.2 V, or VCC(max) = 2.25 V CC current–CMOS inputs (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V, or VIN < 0.2 V, f = 0
ISB2 [8]
–
1
5
A
Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max)=VCC + 0.5 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 8. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance
Parameter [9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter [9] Description JA Thermal resistance (Junction to Ambient) Thermal resistance JC (Junction to case) Test Conditions 48-ball VFBGA Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit 75 C/W board 10 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V
Parameters R1 R2 RTH VTH
1.80 V 13500 10800 6000 0.80
Unit V
Note 9. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR
[11]
Description VCC for data retention Data retention current
Conditions VCC = 1.0 V, CE > VCC – 0.2 V, or (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V
Min 1.0 –
Typ [10] – 1
Max – 4
Unit V A
tCDR [12] tR [13]
Chip deselect to data retention time Operation recovery time
0 55
– –
– –
ns ns
Data Retention Waveform
Figure 3. Data Retention Waveform [14] VCC(min)
tCDR DATA RETENTION MODE VDR > 1.0 V
VCC CE or BHE.BLE
VCC(min)
tR
Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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Switching Characteristics
Over the Operating Range Parameter [15, 16] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle [19] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to high Z [17, 18] WE HIGH to low Z [17] 45 35 35 0 0 35 35 25 0 – 10 – – – – – – – – – 18 – ns ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z [17] OE HIGH to high Z [17, 18] CE LOW to low Z
[17]
Description
55 ns Min Max
Unit
55 – 10 – – 5 – 10 – 0 – – 10 –
– 55 – 55 25 – 18 – 18 – 55 55 – 18
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to high Z [17, 18] CE LOW to power up CE HIGH to power down BLE/BHE LOW to data valid BLE/BHE LOW to low Z [17] BLE/BHE HIGH to high Z [17, 18]
Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 4. Read Cycle No.1 (Address Transition Controlled) [20, 21]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 20. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 21. WE is HIGH for read cycle. 22. Address valid before or similar to CE and BHE, BLE transition LOW.
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Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA I/O NOTE 25 tHZOE
tSD DATAIN
tHD
Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 25 tHZOE DATAIN tHD
Notes 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals.
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Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled) [26]
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA I/O NOTE 27 tHZWE DATAIN
tHD
tLZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [26]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA I/O
NOTE 27
Notes 26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state. Do not apply input signals.
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Truth Table
CE H X[28] L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X
[28]
BLE X
[28]
Inputs or Outputs High Z High Z Data out (I/O0–I/O15) Data out (I/O0–I/O7); I/O8–I/O15 in High Z Data out (I/O8–I/O15); I/O0–I/O7 in High Z High Z High Z High Z Data in (I/O0–I/O15) Data in (I/O0–I/O7); I/O8–I/O15 in High Z Data in (I/O8–I/O15); I/O0–I/O7 in High Z
Mode Deselect or power down Deselect or power down Read Read Read Output disabled Output disabled Output disabled Write Write Write
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
H L H L L H L L H L
H L L H L L H L L H
Note 28. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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Ordering Information
Speed (ns) 55 Ordering Code CY62137FV18LL-55BVXI Package Diagram Package Type Operating Range Industrial 51-85150 48-ball VFBGA (Pb-free)
Contact your local Cypress sales representative for availability of other parts.
Ordering Code Definitions
CY 621 3 7 F V18 LL - 55 BV X I
Temperature Grade: I = Industrial Pb-free Package Type: BV = 48-ball VFBGA Speed Grade: 55 ns Low Power Voltage Range: 1.8 V typical Process Technology: 90 nm Bus width = × 16 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress
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Package Diagram
Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150
51-85150 *F
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CY62137FV18 MoBL®
Acronyms
Acronym BHE BLE CE CMOS I/O OE SRAM VFBGA WE byte high enable byte low enable chip enable complementary metal oxide semiconductor input/output output enable static random access memory very fine-pitch ball grid array write enable Description
Document Conventions
Units of Measure
Symbol °C MHz A s mA mm ns % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure
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Document History Page
Document Title: CY62137FV18 MoBL®, 2-Mbit (128 K × 16) Static RAM Document Number: 001-08030 REV. ** *A *B ECN NO. Submission Date 463660 469180 569125 See ECN See ECN See ECN Orig. of Change NXR NSI NXR New datasheet Minor change: moved to external web Converted from preliminary to final Replaced 45 ns speed bin with 55 ns speed bin Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 A to 1 A Changed the ISB2(max) value from 2.5 A to 5 A Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A to 4 A Added footnote #12 related to tACE Added footnote #8 related to ISB2 and ICCDR Made footnote #13 applicable to AC parameters from tACE Changed tWC specification from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW specification from 35 ns to 40 ns Changed tHZWE specification from 18 ns to 20 ns Description of Change
*C *D
869500 908120
See ECN See ECN
VKN VKN
*E
1274728
See ECN
VKN/AESA Changed tWC specification from 55 ns to 45 ns Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns Changed tHZWE specification from 20 ns to 18 ns VKN Added Contents Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagram Added Sales, Solutions, and Legal Information Added Contents Added Acronyms and Units of Measure Update Package Diagram from *E to *F Added Ordering Code Definitions details. Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature Minor Changes: Corrected CE to CE and WE to WE in Figures 7 and 8 Replaced CE and OE with CE and OE in all instances in page 1. Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated in new template.
*F
2943752
06/03/2010
*G
3055165
10/12/2010
RAME
*H *I
3061313 3263825
10/15/2010 06/17/2011
RAME RAME
Document #: 001-08030 Rev. *I
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08030 Rev. *I
Revised June 17, 2011
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