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CY62137VLL-70ZI

CY62137VLL-70ZI

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

  • 描述:

    CY62137VLL-70ZI - 2-Mbit (128K x 16) Static RAM - Cypress Semiconductor

  • 数据手册
  • 价格&库存
CY62137VLL-70ZI 数据手册
CY62137V MoBL 2-Mbit (128K x 16) Static RAM Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C • • • • • • • • — Automotive: –40°C to 125°C High Speed: 55 ns and 70 ns Wide voltage range: 2.7V–3.6V Ultra-low active, standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package Available in a standard 44-pin TSOP Type II (forward pinout) package also has an automatic power-down feature that reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH) or when CE is LOW and both BLE and BHE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description[1] The CY62137V is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life® (MoBL®) in portable applications such as cellular telephones. The device Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10 ROW DECODER 128K x 16 RAM Array 2048 x 1024 SENSE AMPS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER BHE WE CE OE BLE BHE BLE A11 A12 A13 A14 A15 A16 Power-down Circuit CE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05051 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 21, 2004 CY62137V MoBL Product Portfolio Power Dissipation VCC Range (V) Product CY62137VLL CY62137VSL CY62137VLL CY62137VSL CY62137VLL Automotive Industrial Min. 2.7 Typ.[3] 3.0 Max. 3.6 Speed (ns) 55 55 70 70 70 Operating, ICC (mA) Typ.[3] 7 7 7 7 7 Max. 20 20 15 15 15 Standby, ISB2 (µA) Typ.[3] 1 1 1 1 1 Max. 15 5 15 5 20 Pin Configurations TSOP II (Forward) A4 Top View A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Pin Definitions Pin Number 1-5, 18-22, 24-27, 42-45 23 17 6 39, 40 41 Input No Connect Input/Control Input/Control Input/Control Input/Control Type A0-A16. Address Inputs I/O0-I/O15. Data lines. Used as input or output lines depending on operation NC. This pin is not connected to the die WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip BHE, BLE. BHE = LOW selects higher order byte WRITEs or READs on the SRAM.BLE = LOW selects lower order byte WRITEs or READs on the SRAM OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins Vss. Ground for the device Vcc. Power supply for the device Description 7-10, 13-16, 29-32, 35-38 Input/Output 12, 34 11, 33 Ground Power Supply Notes: 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP)., TA = 25°C. Document #: 38-05051 Rev. *B Page 2 of 11 CY62137V MoBL Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[4] ....................................–0.5V to VCC + 0.5V DC Input Voltage[4] .................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Industrial Automotive Ambient Temperature –40°C to +85°C –40°C to +125°C VCC 2.7V to 3.6V 2.7V to 3.6V Electrical Characteristics Over the Operating Range CY62137V-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Test Conditions VCC = 2.7V VCC = 2.7V 2.2 –0.5 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = 3.6V –1 –1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 20 2.2 –0.5 –1 –1 7 Typ.[3] Output HIGH Voltage IOH = –1.0 mA Output LOW Voltage IOL = 2.1 mA Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current CY62137V-70 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 V V V V µA µA mA Max. Min. Typ.[3] Max. Unit VCC Operating Supply IOUT = 0 mA, Current f = fMAX = 1/tRC, CMOS Levels IOUT = 0 mA, f = 1 MHz, CMOS Levels 1 2 100 1 2 100 mA µA ISB1 Automatic CE Power-down Current— CMOS Inputs Automatic CE Power-down Current— CMOS Inputs CE > VCC – 0.3V, VCC = 3.6V VIN > VCC – 0.3V or VIN < 0.3V, f = fMAX CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 VCC = LL 3.6V Automotive SL 1 1 ISB2 15 5 1 1 1 15 20 5 9 Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC TSOPII 60 22 Unit °C/W °C/W Document #: 38-05051 Rev. *B Page 3 of 11 CY62137V MoBL AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC OUTPUT 5 pF INCLUDING JIG AND SCOPE Equivalent to: (b) R2 R1 VCC Typ GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns Rise Time: 1 V/ns THÉVENIN EQUIVALENT RTH V (a) (c) OUTPUT Parameters R1 R2 RTH VTH 3.0V 1105 1550 645 1.75 Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V LL or VIN < 0.3V; No input may exceed; VCC+0.3V Automotive SL tCDR[5] tR Chip Deselect to Data Retention Time Operation Recovery Time 0 70 Conditions Min. Typ.[3] Max. Unit 1.0 0.5 0.5 7.5 10 5 ns ns V µA Data Retention Waveform VCC CE VCC(min.) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min.) tR Document #: 38-05051 Rev. *B Page 4 of 11 CY62137V MoBL Switching Characteristics Over the Operating Range Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE (9) tHZBE Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBW Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[7, 8] WE HIGH to Low-Z[7] BHE / BLE LOW to End of Write 5 50 55 45 45 0 0 40 25 0 20 10 60 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[7] OE HIGH to High-Z[7, 8] CE LOW to Low-Z[7] CE HIGH to High-Z[7, 8] CE LOW to Power-up CE HIGH to Power-down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low-Z BHE / BLE HIGH to High-Z 5 25 0 55 55 5 25 10 25 0 70 70 5 25 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description [6] 55 ns Min. Max. Min. 70 ns Max. Unit Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30 pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. If both byte enables are toggled together this value is 10 ns. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05051 Rev. *B Page 5 of 11 CY62137V MoBL Switching Waveforms Read Cycle No. 1 [12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 CE [13, 14] tRC tPD tHZCE tACE OE tDOE BHE/BLE tLZOE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tHZOE tHZBE HIGH IMPEDANCE 50% ICC ISB Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05051 Rev. *B Page 6 of 11 CY62137V MoBL Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) ADDRESS [10, 15, 16] tWC CE tAW WE tSA tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 17 tHZOE [10, 15, 16] tHD DATAIN VALID Write Cycle No. 2 (CE Controlled) tWC ADDRESS CE tSA tAW tBW tHA tSCE BHE/BLE WE tPWE tSD tHD DATA I/O Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. DATA VALID IN Document #: 38-05051 Rev. *B Page 7 of 11 CY62137V MoBL Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [11, 16] tWC ADDRESS CE tAW BHE/BLE WE tSA tBW tHA tSD DATA I/O NOTE 17 tHZWE [17] tHD DATA VALID IN tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tAW BHE/BLE tSA WE tSD DATA I/O NOTE 17 tHA tBW tHD DATA VALID IN tHZWE tLZWE Document #: 38-05051 Rev. *B Page 8 of 11 CY62137V MoBL Typical DC and AC Characteristics 1.4 1.2 1.0 ICC 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 35 MoBL 30 25 ISB (µA) 20 15 10 5 0 1.0 2.7 2.8 3.7 1.9 SUPPLY VOLTAGE (V) MoBL Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 1.0 1.9 2.7 2.8 3.7 MoBL SUPPLY VOLTAGE (V) Truth Table CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High-Z High-Z Data Out (I/OO–I/O15) Data Out (I/OO–I/O7); I/O8–I/O15 in High-Z Data Out (I/O8–I/O15); I/O0–I/O7 in High-Z High-Z High-Z High-Z Data In (I/OO–I/O15) Data In (I/OO–I/O7); I/O8–I/O15 in High-Z Data In (I/O8–I/O15); I/O0 –I/O7 in High-Z Mode Deselect/Power-down Deselect/Power-down Read Read Read Deselect/Output Disabled Deselect/Output Disabled Deselect/Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05051 Rev. *B Page 9 of 11 CY62137V MoBL Ordering Information Speed (ns) 55 70 Ordering Code CY62137VLL-55ZI CY62137VSL-55ZI CY62137VLL-70ZI CY62137VSL-70ZI CY62137VLL-70ZE Automotive Package Name Z44 44-pin TSOP II Package Type Operating Range Industrial Package Diagrams 44-Pin TSOP II Z44 PIN 1 I.D. DIMENSION IN MM (INCH) MAX MIN. 22 1 11.938 (0.470) 11.735 (0.462) 10.262 (0.404) 10.058 (0.396) OR E KXA SG 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) BASE PLANE 0°-5° 10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047) 0.597 (0.0235) 0.406 (0.0160) 18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 0.10 (.004) SEATING PLANE 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05051 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62137V MoBL Document Title: CY62137V MoBL® 2M (128K x 16) Static RAM Document Number: 38-05051 REV. ** *A ECN NO. Issue Date 109960 116788 10/03/01 09/04/02 Orig. of Change SZV GBI Description of Change Changed from Spec number: 38-00738 to 38-05051 Added footnote number one. Added SL power bin. Deleted fBGA package; replacement fBGA package is available in CY62137CV30. Added Automotive product information *B 237428 See ECN AJU Document #: 38-05051 Rev. *B Page 11 of 11
CY62137VLL-70ZI 价格&库存

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