2 Mbit (256K x 8) MoBL Static RAM
Features
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CY62138EV30 MoBL®
Functional Description
The CY62138EV30[1] is a high performance CMOS static RAM organized as 256K words by eight bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW).
Very high speed: 45 ns ❐ Wide voltage range: 2.20 V to 3.60 V Pin compatible with CY62138CV30 Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected Complementary metal oxide semiconducor (CMOS) for optimum speed and power Offered in Pb-free 36-ball ball grid array (BGA) package
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Logic Block Diagram
Data in Drivers
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
256K x 8 ARRAY
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note 1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
A12 A13 A14 A15 A16 A17
Cypress Semiconductor Corporation Document #: 38-05577 Rev. *C
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198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised January 17, 2011
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CY62138EV30 MoBL®
Contents
Pin Configuration .............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Electrical Characteristics4.................................................. Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 6 Ordering Information ........................................................ 9 Ordering Code Definition ............................................. 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 10 Document Conventions ................................................. 10 Units of Measure ....................................................... 10 Document History Page ................................................. 11 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12
Document #: 38-05577 Rev. *C
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CY62138EV30 MoBL®
Pin Configuration[2]
FBGA
Top View
A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9
A1 A2
NC WE NC
A3 A4 A5
A6 A7
A8 I/O0 I/O1 Vcc Vss
A B C D E F G H
NC OE A10 CE A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
Product Portfolio
Power Dissipation Product Min CY62138EV30LL 2.2 VCC Range (V) Typ[3] 3.0 Max 3.6 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[3] 2 Max 2.5 15 f = fmax Typ[3] Max 20 Standby ISB2 (A) Typ[3] 1 Max 7
Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
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CY62138EV30 MoBL®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature................................. –65 °C to +150 °C Ambient temperature with power applied ............................................. 55 °C to +125 °C Supply voltage to ground potential ....................................... –0.3 V to VCC(MAX) + 0.3 V DC voltage applied to outputs in High Z state[4,5] ......................... –0.3 V to VCC(MAX) + 0.3 V
DC input voltage[4,5]...................... –0.3 V to VCC(MAX) + 0.3 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA Product CY62138EV30LL Range Ambient Temperature VCC[6]
Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC Operating supply current Automatic CE power down current — CMOS inputs Automatic CE power down current — CMOS inputs Test Conditions IOH = –0.1 mA VCC = 2.20 V IOH = –1.0 mA VCC = 2.70 V IOL = 0.1 mA IOL = 2.1 mA VCC = 2.20 V VCC = 2.70 V CY62138EV30-45 Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 – – – Typ[7] – – – – – – – – – – 15 2 1 Max – – 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 20 2.5 7 Unit V V V V V V V V A A mA mA A
VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, Output disabled f = 1 MHz f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA CMOS levels
ISB1[8]
CE > VCC –0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V), f = fmax (Address and data only), f = 0 (OE, and WE), VCC = 3.60 V CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V
ISB2 [8]
–
1
7
A
Notes 4. VIL(min.) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min.) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C 8. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
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Capacitance
Parameter[9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ.) Max 10 10 Unit pF pF
Thermal Resistance
Parameter[9] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 1. AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board
BGA 72 8.86
Unit C / W C / W
Rise Time: 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH
Parameters R1 R2 RTH VTH
2.50 V 16667 15385 8000 1.20
3.0 V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR [11] tCDR[9] tR[12] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time VCC = 1V, CE > VCC 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Conditions Min 1 – 0 45 Typ[10] – 0.8 – – Max – 3 – – Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE
Notes 9. Tested initially and after any design or process changes that may affect these parameters. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 11. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) 100 s.
VCC (min.) tCDR
VDR > 1.5 V
1.5 V tR
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Switching Characteristics
Over the Operating Range Parameter[13] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[16] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to High Z[14,15] WE HIGH to Low Z
[14]
Description
45 ns Min 45 – 10 – – 5 – 10 – 0 – 45 35 35 0 0 35 25 0 – 10 Max – 45 – 45 22 – 18 – 18 – 45 – – – – – – – – 18 –
Unit
Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to Low Z[14] OE HIGH to High Z[14,15] CE LOW to Low Z[14] CE HIGH to High Z[14,15] CE LOW to power-up CE HIGH to power-up
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 2. Read Cycle No. 1: Address Transition Controlled [17, 18]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes 13. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 15. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 16. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 17. Device is continuously selected. OE, CE = VIL. 18. WE is HIGH for read cycle.
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CY62138EV30 MoBL®
Switching Waveforms
(continued) Figure 3. Read Cycle No. 2: OE Controlled [19, 20]
ADDRESS CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD 50%
[21, 23]
tRC
tHZOE tHZCE
HIGH IMPEDANCE
ICC ISB
Figure 4. Write Cycle No. 1: WE Controlled
tWC ADDRESS tSCE
CE tAW WE tSA
tHA tPWE
OE tSD DATA I/O NOTE 22 tHZOE DATAIN VALID tHD
Notes 19. WE is HIGH for read cycle. 20. Address valid prior to or coincident with CE transition LOW. 21. Data I/O is high impedance if OE = VIH. 22. During this period, the I/Os are in output state and input signals should not be applied. 23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
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Switching Waveforms
(continued) Figure 5. Write Cycle No. 2 CE Controlled [24, 25]
tWC
ADDRESS tSCE CE tSA tAW tPWE WE tHA
OE tSD DATA I/O DATAIN VALID tHD
Figure 6. Write Cycle No. 3 : WE Controlled, OE LOW [25]
tWC
ADDRESS CE
tSCE
tAW tSA WE tPWE tSD
tHA
tHD
DATA I/O
NOTE 26
DATAIN VALID tHZWE tLZWE
Truth Table
CE H
[27]
WE X H H L
OE X L H X High Z
Inputs/Outputs Data out (I/O0–I/O7) High Z Data in (I/O0–I/O7) Read Output disabled Write
Mode Deselect/power-down
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
L L L
Notes 24. Data I/O is high impedance if OE = VIH 25. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 26. During this period, the I/Os are in output state and input signals should not be applied. 27. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
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CY62138EV30 MoBL®
Ordering Information
Speed (ns) 45 Ordering Code CY62138EV30LL-45BVXI Package Diagram 51-85149 Package Type 36-Ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free) Operating Range Industrial
Ordering Code Definition
CY 621 3 8E V30 LL 45 XXX X
Temperature Grades I = Industrial Package Type BVX: VFBGA (Pb-free) Speed Grade Low Power Voltage Range = 3 V typical Bus Width = X8 E = 90nm Technology Density = 2 Mbit MoBL SRAM Family Company ID: CY = Cypress
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CY62138EV30 MoBL®
Package Diagram
Figure 7. 36-Ball VFBGA (6 x 8 x 1 mm) (51-85149)
51-85149-*D
Acronyms
Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball gird array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol °C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
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Document History Page
Document Title: CY62138EV30 MoBL® 2 Mbit (256K x 8) MoBL Static RAM Document Number: 38-05577 Rev. ** *A ECN No. 237432 427817 Orig. of Change AJU NXR Submission Date See ECN See ECN New data sheet Removed 35 ns Speed Bin Removed “L” version Removed 32-pin TSOPII package from product Offering. Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Moved Product Portfolio from Page # 3 to Page #2. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from 2.5 A to 7 A. Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed the AC test load capacitance from 50pF to 30pF on Page# 4 Changed VDR from 1.5V to 1V on Page# 4. Changed ICCDR from 1 A to 3 A in the Data Retention Characteristics table on Page # 4. Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tOHA, tLZCE, tLZWE from 6 ns to 10 ns Changed tHZOE, tHZCE, tHZWE from 15 ns to 18 ns Changed tLZOE from 3 ns to 5 ns Changed tSCE and tAW from 40 ns to 35 ns Changed tSD from 20 ns to 25 ns Changed tPWE from 25 ns to 35 ns Updated the Ordering Information table and replaced Package Name column with Package Diagram. Added footnote 7 related to ISB2 and ICCDR Updated Datasheet as per new template Added Ordering Code Definition Added Acronyms and Units of Measure table Converted all tablenotes to Footnote Updated Package Diagram 51-85149 from *C to *D Description of Change
*B *C
2604685 3143896
VKN/PYRS RAME
11/12/08 01/17/2011
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05577 Rev. *C
Revised January 17, 2011
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