CY62138F MoBL®
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
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Functional Description
The CY62138F is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW). To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW).
High speed: 45 ns Wide voltage range: 4.5 V to 5.5 V Pin compatible with CY62138V Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 5 A Ultra low active power ❐ Typical active current: 1.6 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in Pb-free 32-pin SOIC and 32-pin thin small outline package (TSOP) II packages
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Logic Block Diagram
Cypress Semiconductor Corporation Document #: 001-13194 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised June 20, 2011
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Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Documents Conventions ............................................... 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15
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Pin Configuration
Figure 1. 32-pin SOIC/TSOP II Pinout (Top View)
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
Product Portfolio
Power Dissipation Product Min CY62138FLL 4.5 V VCC Range (V) Typ [1] 5.0 V Max 5.5 V 45 Speed (ns) Operating ICC (mA) f = 1 MHz Typ [1] 1.6 Max 2.5 f = fmax Typ [1] 13 Max 18 Standby ISB2 (A) Typ [1] 1 Max 5
Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ............................. –0.5 V to 6.0 V (VCCmax + 0.5 V) DC voltage applied to outputs in High Z state [2, 3] ............. –0.5 V to 6.0 V (VCCmax + 0.5 V) DC Input Voltage [2, 3] ......... –0.5 V to 6.0 V (VCCmax + 0.5 V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ........................................ > 2001 V (MIL–STD–883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Device CY62138FLL Range Industrial Ambient Temperature VCC [4] –40 °C to +85 °C 4.5 V to 5.5 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB2 [6] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply Current Test Conditions IOH = –1.0 mA IOL = 2.1 mA VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V GND < VI < VCC GND < VO < VCC, Output disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max), IOUT = 0 mA, CMOS levels 45 ns Min 2.4 – 2.2 –0.5 –1 –1 – – – Typ [5] – – – – – – 13 1.6 1 Max – 0.4 VCC + 0.5 0.8 +1 +1 18 2.5 5 A Unit V V V V A A mA
Automatic CE Power-down CE1 > VCC – 0.2 V or CE2 < 0.2 V, current CMOS inputs VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max)
Notes 2. VIL(min) = –2.0 V for pulse durations less than 20 ns. 3. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 4. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 6. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance
Parameter [7] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter [7] JA JC Description Thermal resistance (Junction to Ambient) Thermal resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch two-layer printed circuit board 32-pin SOIC 44.53 24.05 32-pin TSOP II Unit 44.16 11.97 C/W C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms R1 3.0 V 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10%
VCC OUTPUT
ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters R1 R2 RTH VTH
5.0 V 1800 990 639 1.77
Unit V
Note 7. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR
[9]
Description VCC for Data retention Data retention current Chip deselect to data retention time Operation recovery time
Conditions VCC = VDR, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V
Min 2.0 – 0 45
Typ [8] – 1 – –
Max – 5 – –
Unit V A ns ns
tCDR [8] tR [10]
Data Retention Waveform
Figure 3. Data Retention Waveform [11]
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 2.0 V
VCC(min)
tR
CE
Notes 8. Tested initially and after any design or process changes that may affect these parameters. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
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Switching Characteristics
Over the Operating Range Parameter [12] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[15]
Description
45 ns Min Max
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to low Z
[13] [13, 14] [13]
45 – 10 – – 5 – 10 – 0 –
– 45 – 45 22 – 18 – 18 – 45
ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to high Z
CE1 LOW and CE2 HIGH to low Z
CE1 HIGH or CE2 LOW to high Z [13, 14] CE1 LOW and CE2 HIGH to power-up CE1 HIGH or CE2 LOW to power-down Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z [13, 14] WE HIGH to low Z
[13]
45 35 35 0 0 35 25 0 – 10
– – – – – – – – 18 –
ns ns ns ns ns ns ns ns ns ns
Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE , tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [17, 18, 19]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Figure 6. Write Cycle No. 1 (WE Controlled) [19, 20, 21, 22]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 23 tHZOE
Notes 16. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 19. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 21. Data I/O is high impedance if OE = VIH. 22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 23. During this period, the I/Os are in output state. Do not apply input signals.
tHD
DATA VALID
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Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [24, 25, 26, 27]
tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
CE
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [24, 27]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 28 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Notes 24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals.
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Truth Table
CE1 H X[29] L L L CE2 X
[29]
WE X X H H L
OE X X L H X
Inputs/Outputs High Z High Z Data out High Z Data in
Mode Deselect/Power-down Deselect/Power-down Read Output disabled Write
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
L H H H
Note 29. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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CY62138F MoBL®
Ordering Information
Speed (ns) 45 Ordering Code CY62138FLL-45SXI CY62138FLL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) 51-85095 32-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 3 8 F LL - 45 XX X I
Temperature Grade: I = Industrial Pb-free Package Type: XX = S or ZS S = 32-pin SOIC ZS = 32-pin TSOP II Speed Grade: 45 ns LL = Low Power F = Process Technology 90 nm Bus width = × 8 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress
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Package Diagrams
Figure 9. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
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Package Diagrams (continued)
Figure 10. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32, 51-85095
51-85095 *B
Acronyms
Acronym CMOS I/O OE SOIC SRAM TSOP WE input/output output enable small outline integrated circuit static random access memory thin small outline package write enable Description complementary metal oxide semiconductor
Documents Conventions
Units of Measure
Symbol °C MHz A s mA ns % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes nano seconds ohms percent pico Farads Volts Watts Unit of Measure
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Document History Page
Document Title: CY62138F MoBL®, 2-Mbit (256 K × 8) Static RAM Document Number: 001-13194 REV. ** *A *B ECN NO. Issue Date 797956 940341 3055174 See ECN See ECN 13/10/2010 Orig. of Change VKN VKN RAME Description of Change New Data Sheet Added footnote #7 related to ISB2 and ICCDR Updated As per new template Added Acronyms and Units of Measure table. Added Ordering Code Definitions. Footnotes updated Updated Package Diagram Figure 9 and Figure 10. Minor change: Corrected “IO” to “I/O” Removed the Note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com ” in page 1. Updated Package Diagrams. Updated in new template.
*C *D
3061313 3232735
15/10/2010 04/18/2011
RAME RAME
*E
3287636
06/20/2011
RAME
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13194 Rev. *E
Revised June 20, 2011
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MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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