CY62146DV30L-55BVXI

CY62146DV30 4-Mbit (256K x 16) Static RAM Features • Very high speed: 45 ns • Wide voltage range: 2.20V–3.60V • Pin-compatible with CY62146CV30 • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 8 mA @ f = fmax • Ultra low standby power • Easy memory expansion with CE, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered 48-ball BGA and 44-pin TSOPII • Also available in Lead-free packages an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62146DV30 is available in a 48-ball VFBGA, 44-pin TSOPII packages. Functional Description[1] The CY62146DV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A11 A12 A13 A14 A15 A16 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. A17 Cypress Semiconductor Corporation Document #: 38-05339 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 2, 2005 CY62146DV30 Pin Configuration[2, 3, 4] 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 VFBGA (Top View) 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H 44 TSOP II (Top View) I/O12 DNU I/O13 NC A8 A14 A12 A9 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Operating ICC (mA) VCC Range (V) Product CY62146DV30L CY62146DV30LL CY62146DV30L CY62146DV30LL CY62146DV30L CY62146DV30LL Notes: 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating or tied to VSS to ensure proper application. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Min. 2.20V 2.20V 2.20V Typ.[5] 3.0 3.0 3.0 Max. 3.60 3.60 3.60 Speed (ns) 45 55 70 f = 1MHz Typ.[5] 1.5 1.5 1.5 Max. 3 3 3 f = fmax Typ.[5] 10 8 8 Max. 20 15 15 Standby ISB2 (µA) Typ.[5] 2 2 2 Max. 12 8 12 8 12 8 Document #: 38-05339 Rev. *A Page 2 of 11 CY62146DV30 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ......................................–0.3V to + VCC(MAX) + 0.3V DC Voltage Applied to Outputs in High-Z State[6, 7] .........................–0.3V to VCC(MAX) + 0.3V DC Input Voltage[6, 7] ..................... –0.3V to VCC(MAX) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Device CY62146DV30L CY62146DV30LL Range Ambient Temperature (TA) VCC[8] Industrial –40°C to +85°C 2.20V to 3.60V Electrical Characteristics Over the Operating Range CY62146DV30-45 Parameter Description VOH VOL VIH Test Conditions Min. Typ.[5] 2.0 2.4 0.4 0.4 1.8 2.2 –0.3 –0.3 –1 –1 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 1.8 2.2 –0.3 –0.3 –1 –1 Max. Output HIGH IOH = –0.1 mA VCC = 2.20V Voltage IOH = –1.0 mA VCC = 2.70V Output LOW IOL = 0.1 mA VCC = 2.20V Voltage IOL = 2.1 mA VCC = 2.70V Input HIGH Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VIL IIX IOZ ICC Input LOW Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V CY62146DV30-55 Min. Typ.[5] 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 1.8 2.2 –0.3 –0.3 –1 –1 Max. CY62146DV30-70 Min. Typ.[5] Max. Unit 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 V V V V V V V V µA µA Input Leakage GND < VI < VCC Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current — CMOS Inputs GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels 10 1.5 2 20 3 12 8 8 1.5 2 15 3 12 8 8 1.5 2 15 3 12 8 mA mA µA ISB1 CE > VCC−0.2V, L VIN>VCC–0.2V, VIN VCC – 0.2V, Automatic L CE VIN > VCC – 0.2V or VIN < LL Power-down 0.2V, Current — f = 0, VCC = 3.60V CMOS Inputs 2 12 8 2 12 8 2 12 8 µA Notes: 6. VIL(min.) = –2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 8. Full device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. Document #: 38-05339 Rev. *A Page 3 of 11 CY62146DV30 Capacitance (for all packages)[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 10 10 Unit pF pF Thermal Resistance[9] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board BGA 72 8.86 TSOP II 75.13 8.95 Unit °C/W °C/W AC Test Loads and Waveforms[10] VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R1 VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉ VENIN EQUIVALENT RTH OUTPUT V 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V L LL 0 tRC Conditions Min. 1.5 9 6 ns ns Typ.[5] Max. Unit V µA tCDR[9] tR[11] Chip Deselect to Data Retention Time Operation Recovery Time Data Retention Waveform VCC CE VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V VCC(min) tR Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. Test condition for the 45 ns part is a load capacitance of 30 pF. 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05339 Rev. *A Page 4 of 11 CY62146DV30 Switching Characteristics Over the Operating Range [12] 45 ns[10] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[15] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[13, 14] [13] 55 ns Min. 55 Max. Min. 70 55 10 10 55 25 5 5 20 10 10 20 0 0 55 25 10 10 20 55 40 40 0 0 40 40 25 0 70 60 60 0 0 45 60 30 0 20 10 10 70 ns Max. Unit ns 70 70 35 25 25 70 35 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z [13] Min. 45 Max. 45 10 45 25 5 15 10 20 0 45 25 10 15 45 40 40 0 0 35 40 25 0 15 10 OE HIGH to High Z[13, 14] CE LOW to Low Z[13] CE HIGH to High Z[13, 14] CE LOW to Power-Up CE HIGH to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[13] Z[13, 14] BLE/BHE HIGH to HIGH WE HIGH to Low-Z Notes: 12. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05339 Rev. *A Page 5 of 11 CY62146DV30 Switching Waveforms Read Cycle 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled)[17, 18] ADDRESS CE tACE OE tDOE BHE/BLE tLZOE tRC tPD tHZCE tHZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE Notes: 16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE and BHE, BLE transition LOW. Document #: 38-05339 Rev. *A Page 6 of 11 CY62146DV30 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[15, 19, 20] tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 21 tHZOE DATAIN tHD Write Cycle No. 2 (CE Controlled)[15, 19, 20] tWC ADDRESS tSCE CE tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA I/O NOTE 21 tHZOE Notes: 19. Data I/O is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 21. During this period, the I/Os are in output state and input signals should not be applied. tHD DATAIN Document #: 38-05339 Rev. *A Page 7 of 11 CY62146DV30 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[20] tWC ADDRESS tSCE CE tBW tAW tSA WE tSD DATA I/O NOTE 21 tHZWE DATAIN tLZWE tHD tPWE tHA BHE/BLE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tHZWE tHA tBW tPWE tSD DATAIN tLZWE tHD DATA I/O NOTE 21 Document #: 38-05339 Rev. *A Page 8 of 11 CY62146DV30 Truth Table CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO–I/O15) Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Data Out (I/O8–I/O15); I/O0–I/O7 in High Z High Z High Z High Z Data In (I/OO–I/O15) Data In (I/OO–I/O7); I/O8–I/O15 in High Z Data In (I/O8–I/O15); I/O0–I/O7 in High Z Mode Deselect/Power-Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62146DV30LL-45BVI CY62146DV30LL-45BVXI CY62146DV30LL-45ZSXI 55 CY62146DV30L-55BVI CY62146DV30L-55BVXI CY62146DV30LL-55BVI CY62146DV30LL-55BVXI CY62146DV30L-55ZSXI CY62146DV30LL-55ZSXI 70 CY62146DV30L-70BVI CY62146DV30L-70BVXI CY62146DV30LL-70BVI CY62146DV30LL-70BVXI CY62146DV30L-70ZSXI CY62146DV30LL-70ZSXI ZS-44 BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 44-pin TSOP II (Pb-free) Industrial Industrial ZS-44 ZS-44 BV48A Package Name BV48A Package Type 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 44-pin TSOP II (Pb-free) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 44-pin TSOP II (Pb-free) Industrial Operating Range Industrial Document #: 38-05339 Rev. *A Page 9 of 11 CY62146DV30 Package Diagram 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 44-Pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05339 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62146DV30 Document History Page Document Title:CY62146DV30 MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 38-05339 REV. ** *A ECN NO. Issue Date 213251 316039 See ECN See ECN Orig. of Change AJU PCI New Data Sheet Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #10 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-lead TSOP-II package name on page 10 from Z44 to ZS44 Standardized Icc values across ‘L’ and ‘LL’ bins Description of Change Document #: 38-05339 Rev. *A Page 11 of 11