CY62146E MoBL®
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
■
Very high speed: 45 ns
■
Wide voltage range: 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP)
Type II package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 11 for a
complete description of read and write modes.
Functional Description
The CY62146E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please Electrical Characteristics on
page 4 for more details and suggested alternatives.
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL®) in portable
applications. The device also has an automatic power down
feature that reduces power consumption when addresses are
For a complete list of related documentation, click here.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 001-07970 Rev. *O
•
BHE
WE
CE
OE
BLE
A17
A16
A15
A13
A14
A12
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 29, 2019
CY62146E MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-07970 Rev. *O
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62146E MoBL®
Pin Configurations
Figure 1. 44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Product Portfolio
Power Dissipation
Product
CY62146ELL
VCC Range (V)
Range
Industrial /
Automotive-A
Speed
(ns)
Min
Typ [2]
Max
4.5
5.0
5.5
45
Operating ICC, (mA)
f = 1 MHz
f = fmax
Standby, ISB2
(A)
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-07970 Rev. *O
Page 3 of 17
CY62146E MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch-up current ..................................................... >200 mA
Operating Range
Supply voltage to ground potential ................–0.5 V to 6.0 V
Device
DC voltage applied to outputs
in high Z state [3, 4] .........................................–0.5 V to 6.0 V
CY62146ELL
Range
Ambient
Temperature
VCC[5]
Industrial/
–40 °C to +85 °C 4.5 V–5.5 V
Automotive-A
DC input voltage [3, 4] .....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output high voltage
Test Conditions
VCC = 4.5 V
VCC = 5.5 V
IOH = –1.0 mA
Min
Typ[6]
Max
2.4
–
–
V
[7]
–
–
–
0.4
V
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
V
Input low voltage
4.5 < VCC < 5.5
–0.5
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
–
15
20
mA
–
2
2.5
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
1
7
Output low voltage
IOL = 2.1 mA
VIH
Input high voltage
VIL
f = 1 MHz
ISB2 [8]
Automatic CE power down
current – CMOS inputs
3.4
Unit
–
VOL
IOH = –0.1 mA
45 ns (Industrial/Automotive-A)
A
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs are left floating.
Document Number: 001-07970 Rev. *O
Page 4 of 17
CY62146E MoBL®
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
55.52
C/W
16.03
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
VCC
10%
GND
R2 Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
5.0 V
Unit
R1
1800
R2
990
RTH
639
VTH
1.77
V
Note
9. Tested initially after any design or process changes that may affect these parameters.
Document Number: 001-07970 Rev. *O
Page 5 of 17
CY62146E MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ [10]
Max
Unit
2
–
–
V
–
1
7
A
VDR
VCC for data retention
ICCDR [11]
Data retention current
tCDR [12]
Chip deselect to data retention
time
0
–
–
ns
tR [13]
Operation recovery time
45
–
–
ns
VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2.0 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs are left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-07970 Rev. *O
Page 6 of 17
CY62146E MoBL®
Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
45 ns (Industrial/Automotive-A)
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z[16]
5
–
ns
–
18
ns
10
–
ns
–
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low
Z[16, 17]
Z[16]
Z[16, 17]
tHZCE
CE HIGH to High
18
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
22
ns
ns
Z[16]
tLZBE
BLE/BHE LOW to Low
5
–
tHZBE
BLE/BHE HIGH to High Z[16, 17]
–
18
ns
Write cycle time
45
–
ns
ns
Write
tWC
Cycle[18, 19]
tSCE
CE LOW to write end
35
–
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
ns
tPWE
WE pulse width
35
–
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
[16, 17]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z [16]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in Figure 2 on page 5.
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-07970 Rev. *O
Page 7 of 17
CY62146E MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-07970 Rev. *O
Page 8 of 17
CY62146E MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 26
tHD
DATAIN
tHZOE
Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 26
tHZOE
Notes
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate the write by going inactive. The input setup and hold timing must be referenced to the edge of the signal that terminate the write.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-07970 Rev. *O
Page 9 of 17
CY62146E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28, 30]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 29
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [27, 28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tHD
DATAIN
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate the write by going inactive. The input setup and hold timing must be referenced to the edge of the signal that terminate the write.
29. During this period, the I/Os are in output state. Do not apply input signals.
30. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 001-07970 Rev. *O
Page 10 of 17
CY62146E MoBL®
Truth Table
CE[31]
WE
OE
BHE
BLE
[31]
[31]
High Z
Deselect/power down
Standby (ISB)
X
X
Inputs/Outputs
Mode
Power
H
X
X
L
X
X
H
H
High Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
31. Chip enable (CE) and byte enables (BHE and BLE) must be at CMOS levels (not floating) to meet the ISB2 / ICCDR spec. Intermediate voltage levels on these pins is
not permitted.
Document Number: 001-07970 Rev. *O
Page 11 of 17
CY62146E MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62146ELL-45ZSXI
Package Type
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 4
6
E
LL - 45
ZS
X
X
Temperature Range: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type:
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-07970 Rev. *O
Page 12 of 17
CY62146E MoBL®
Package Diagram
Figure 10. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-07970 Rev. *O
Page 13 of 17
CY62146E MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory
ohm
TSOP
Thin Small Outline Package
pF
picofarad
VFBGA
Very Fine-Pitch Ball Gird Array
V
volt
WE
Write Enable
W
watt
Document Number: 001-07970 Rev. *O
Symbol
Unit of Measure
Page 14 of 17
CY62146E MoBL®
Document History Page
Document Title: CY62146E MoBL®, 4-Mbit (256K × 16) Static RAM
Document Number: 001-07970
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
463213
NXR
05/19/2006
New data sheet.
*A
684343
VKN
01/17/2007
Added Automotive-A Temperature Range related information in all instances
across the document and made the information Preliminary (by shading in
required places).
Updated Ordering Information:
Updated part numbers.
*B
925501
VKN
04/09/2007
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
*C
1045260
VKN
05/07/2007
Changed status of Automotive-A Temperature Range related information from
Preliminary to Final (by unshading in required places).
Updated Ordering Information:
No change in part numbers.
Unshaded the Automotive-A MPNs (Changed status from Preliminary to Final).
*D
2073548
VKN /
AESA
02/06/2008
Updated Data Retention Waveform:
Updated Figure 3 (Corrected typo).
Removed Note “BHE. BLE is the AND of BHE and BLE. Deselect the chip by
either disabling the chip enable signals or by disabling BHE and BLE.” and its
reference.
Updated to new template.
*E
2943752
VKN
06/03/2010
Updated Truth Table:
Added Note 31 and referred the same note in “CE” column.
Updated Package Diagram:
spec 51-85087 – Changed revision from *A to *C.
Updated to new template.
*F
3109050
PRAS
12/13/2010
Changed Table Footnotes to Notes in all instances across the document.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
*G
3149059
RAME
01/20/2011
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions (Corrected Errors).
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*H
3296704
RAME
06/29/2011
Updated Functional Description:
Updated description (Removed “For best practice recommendations, refer to
the Cypress application note AN1064, SRAM System Guidelines.”).
*I
3921993
MEMJ
03/05/2013
Updated Switching Waveforms:
Added Note 25 and referred the same note in Figure 6, Figure 7.
Removed Note “WE is HIGH for read cycle.” and its references in Figure 6,
Figure 7.
Added Note 28 and referred the same note in Figure 8, Figure 9.
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *E.
Completing Sunset Review.
Document Number: 001-07970 Rev. *O
Description of Change
Page 15 of 17
CY62146E MoBL®
Document History Page (continued)
Document Title: CY62146E MoBL®, 4-Mbit (256K × 16) Static RAM
Document Number: 001-07970
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*J
4013949
MEMJ
06/04/2013
Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter
and added maximum value corresponding to that Test Condition.
Added Note 7 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “VCC = 5.5 V, IOH = –0.1 mA”.
*K
4102022
VINI
08/14/2013
Updated Switching Characteristics:
Updated Note 15.
Updated to new template.
*L
4576478
VINI
11/21/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 30 and referred the same note in Figure 8.
*M
5196888
VINI
04/14/2016
Updated Thermal Resistance:
Updated values of JA and JC parameters in “44-pin TSOP II” column.
Updated to new template.
Completing Sunset Review.
*N
6049346
VINI
01/29/2018
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
*O
6560791
VINI
04/29/2019
Updated to new template.
Document Number: 001-07970 Rev. *O
Page 16 of 17
CY62146E MoBL®
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-07970 Rev. *O
Revised April 29, 2019
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation.
Page 17 of 17
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