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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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CY62146EV30 MoBL
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life™ (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62146DV30
■
Ultra low standby power
❐ Typical standby current: 2.5 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in a Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin TSOP II Packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
For a complete list of related documentation, click here.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 38-05567 Rev. *O
•
BHE
WE
CE
OE
BLE
A17
A16
A15
A13
A14
A12
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY62146EV30 MoBL
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05567 Rev. *O
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY62146EV30 MoBL
Pin Configurations
Figure 1. 48-ball VFBGA pinout [1, 2]
Figure 2. 44-pin TSOP II pinout [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
A17
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Product Portfolio
Power Dissipation
Product
CY62146EV30LL
VCC Range (V)
Range
Industrial/
Automotive-A
Min
Typ [3]
Max
2.2
3.0
3.6
Speed
(ns)
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
3.5
6
15
20
2.5
7
Notes
1. NC pins are not connected on the die.
2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8Mb, 16Mb and 32Mb respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05567 Rev. *O
Page 3 of 19
CY62146EV30 MoBL
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC max + 0.3 V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Output current into outputs (LOW) ............................. 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up Current .................................................... >200 mA
Operating Range
Supply voltage
to ground potential .......... –0.3 V to + 3.9 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High-Z state [4, 5] ............ –0.3 V to 3.9 V (VCCmax + 0.3 V)
Device
CY62146EV30
Range
Ambient
Temperature
VCC [6]
Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V
Automotive-A
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input LOW Voltage
Test Conditions
45 ns (Industrial/Automotive-A)
Unit
Min
Typ [7]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
–
15
20
mA
–
3.5
6
–
2.5
7
A
–
2.5
7
A
f = 1 MHz
ISB1
Automatic CE power down
current – CMOS inputs
VCC = VCC(max),
IOUT = 0 mA
CMOS levels
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
ISB2 [8]
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 38-05567 Rev. *O
Page 4 of 19
CY62146EV30 MoBL
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
VFBGA
TSOP II
Unit
42.10
55.52
C/W
23.45
16.03
C/W
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
All Input Pulses
VCC
Output
10%
R2
30 pF
Including
JIG and
Scope
90%
10%
90%
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: Thevenin Equivalent
Output
RTH
VTH
Parameter
2.50 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05567 Rev. *O
Page 5 of 19
CY62146EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
VCC for data retention
[11]
Data retention current
VCC = 1.5 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
Industrial/
Automotive-A
Min
Typ [10]
Max
Unit
1.5
–
–
V
–
3
8.8
A
tCDR [12]
Chip deselect to data retention
time
–
0
–
–
ns
tR [13]
Operation recovery time
–
45
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 38-05567 Rev. *O
Page 6 of 19
CY62146EV30 MoBL
Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
45 ns
(Industrial/Automotive-A)
Min
Unit
Max
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[16]
5
–
ns
–
18
ns
10
–
ns
–
18
ns
–
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z [16, 17]
tLZCE
tHZCE
CE LOW to Low-Z
[16]
CE HIGH to High-Z
[16, 17]
tPU
CE LOW to power up
0
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE / BHE LOW to data valid
–
22
ns
[16]
5
–
ns
–
18
ns
tLZBE
tHZBE
Write Cycle
BLE / BHE LOW to Low-Z
BLE / BHE HIGH to High-Z
[16, 17]
[18, 19]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
Address setup to write end
35
–
ns
tAW
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
–
ns
tSD
BLE / BHE LOW to write end
Data setup to write end
35
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
tBW
tHZWE
tLZWE
WE LOW to High-Z
[16, 17]
WE HIGH to Low-Z
[16]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
19. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 38-05567 Rev. *O
Page 7 of 19
CY62146EV30 MoBL
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA I/O
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05567 Rev. *O
Page 8 of 19
CY62146EV30 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 26
tHD
DATAIN
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 26
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *O
Page 9 of 19
CY62146EV30 MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 29
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [27]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tHD
DATAIN
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
29. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *O
Page 10 of 19
CY62146EV30 MoBL
Truth Table
CE [30]
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/power-down
Standby (ISB)
L
X
X
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Inputs/Outputs
Mode
Power
Note
30. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05567 Rev. *O
Page 11 of 19
CY62146EV30 MoBL
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62146EV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62146EV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Please contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
CY 621 4
6
E V30 LL - 45 XX
X
X
Temperature Grade: X = I
I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = VFBGA; ZS = TSOP II
Speed Grade: 45 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05567 Rev. *O
Page 12 of 19
CY62146EV30 MoBL
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 38-05567 Rev. *O
Page 13 of 19
CY62146EV30 MoBL
Package Diagrams (continued)
Figure 12. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 38-05567 Rev. *O
Page 14 of 19
CY62146EV30 MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
CE
Chip Enable
A
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory
ohm
TSOP
Thin Small Outline Package
pF
picofarad
VFBGA
Very Fine-Pitch Ball Gird Array
V
volt
WE
Write Enable
W
watt
Document Number: 38-05567 Rev. *O
Symbol
Unit of Measure
Page 15 of 19
CY62146EV30 MoBL
Document History Page
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Rev.
ECN No.
Submission
Date
**
223225
05/05/2004
New data sheet.
*A
247373
07/28/2004
Changed status from Advance Information to Preliminary.
Updated Operating Range:
Updated Note 6 (Replaced “100 s wait time” with “200 s wait time”).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.0 A to 2.5 A.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bin.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE, tHZBE, and tHZWE parameters from 12 ns to 15 ns
corresponding 35 ns speed bin and from 15 ns to 18 ns corresponding to 45 ns speed bin.
Changed maximum value of tHZCE parameter from 12 ns to 18 ns corresponding to 35 ns
speed bin and from 15 ns to 22 ns corresponding to 45 ns speed bin.
Changed maximum value of tDBE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed minimum value of tSCE and tBW parameters from 25 to 30 ns corresponding to
35 ns speed bin and from 40 ns to 35 ns corresponding to 45 ns speed bin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed
bin and from 20 ns to 22 ns corresponding to 45 ns speed bin.
Removed Note “If both Byte Enables (BHE and BLE) are toggled together then this value
is 6 ns min. Otherwise this value is 3 ns min.” and its reference in tLZBE parameter.
Updated Ordering Information:
Updated part numbers.
*B
414807
12/16/2005
Changed status from Preliminary to Final.
Removed “L” version of CY62146EV30 part in all instances across the document.
Removed 35 ns speed bin related information in all instances across the document.
Changed the address of Cypress Semiconductor Corporation in Page 1 from “3901 North
First Street” to “198 Champion Court”.
Updated Pin Configurations:
Updated Figure 1 (Replaced DNU with NC corresponding to ball E3).
Removed Note “DNU pins have to be left floating or tied to VSS to ensure proper application.”
and its reference.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 12 mA to 15 mA corresponding to 45 ns speed
bin and Test Condition “f = fmax”.
Changed typical value of ICC parameter from 1.5 mA to 2 mA corresponding to 45 ns speed
bin and Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2 mA to 2.5 mA corresponding to 45 ns
speed bin and Test Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 0.7 A to 1 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB1 parameter from 2.5 A to 7 A corresponding to 45 ns
speed bin.
Changed typical value of ISB2 parameter from 0.7 A to 1 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB2 parameter from 2.5 A to 7 A corresponding to 45 ns
speed bin.
Updated AC Test Loads and Waveforms:
Updated Figure 3 (Replaced 50 pF with 30 pF).
Document Number: 38-05567 Rev. *O
Description of Change
Page 16 of 19
CY62146EV30 MoBL
Document History Page (continued)
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Rev.
ECN No.
Submission
Date
Description of Change
*B (cont.)
414807
12/16/2005
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.5 A to 7 A.
Added typical value of ICCDR parameter.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tLZBE parameter from 6 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tPWE parameter from 30 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSD parameter from 22 ns to 25 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *B to *D.
Updated to new template.
*C
925501
04/09/2007
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
*D
2678796
03/25/2009
Added Automotive-A Temperature Range related information in all instances across the
document.
Completing Sunset Review.
*E
2944332
06/04/2010
Updated Truth Table:
Added Note 30 and referred the same note in “CE” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *A to *C.
Updated to new template.
*F
3109050
12/13/2010
Changed all Table Footnotes to Notes in all instances across the document.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *E to *F.
*G
3302915
07/14/2011
Updated Functional Description:
Removed “For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.” at the end.
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions.
Added Units of Measure.
Updated to new template.
Document Number: 38-05567 Rev. *O
Page 17 of 19
CY62146EV30 MoBL
Document History Page (continued)
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Rev.
ECN No.
Submission
Date
*H
3961126
04/10/2013
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Completing Sunset Review.
*I
4101995
08/22/2013
Updated Switching Characteristics:
Updated Note 15.
Updated to new template.
*J
4348752
04/16/2014
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 28 and referred the same note in Figure 9 (for tPWE parameter in WE Controlled,
OE LOW Write Cycle).
Completing Sunset Review.
*K
4576526
11/21/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*L
5233278
04/21/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated all values in “VFBGA” and “TSOP II” columns.
Updated to new template.
Completing Sunset Review.
*M
6029183
01/12/2018
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*N
6560465
04/29/2019
Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Completing Sunset Review.
*O
6906316
06/26/2020
Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to
“f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.8 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagrams:
spec 51-85087 – Changed revision from *E to *F.
Updated to new template.
Document Number: 38-05567 Rev. *O
Description of Change
Page 18 of 19
CY62146EV30 MoBL
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
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by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
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medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05567 Rev. *O
Revised June 26, 2020
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor Corporation.
Page 19 of 19
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