CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
4-Mbit (256K words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed: 45 ns/55 ns
■
Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
■
Embedded ECC for single-bit error correction[1]
■
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY62146G/CY62146GE and CY62146GSL/CY62146GESL are
high-performance CMOS low-power (MoBL) SRAM devices with
embedded ECC. Both devices are offered in single and dual chip
enable options and in multiple pin configurations. The
CY62146GE/CY62146GESL device includes an ERR pin that
signals an error-detection and correction event during a read
cycle. The CY62146GSL/CY62146GESL[1] device supports a
wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are deasserted (OE, BLE, BHE).
On the CY62146GE/CY62146GESL devices, the detection and
correction of a single-bit error in the accessed location is
indicated by the assertion of the ERR output (ERR = HIGH)[2].
See
the
Truth
Table
–
CY62146G/CY62146GE/CY62146GSL/CY62146GESL
on
page 17 for a complete description of read and write modes.
The logic block diagrams are on page 2.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
Product Portfolio
Product[3]
CY62146G(E)18
CY62146G(E)30
Features and
Options
(see the Pin
Configurations
section)
Single or dual
Chip Enables
Power Dissipation
Range
Industrial
CY62146G(E)
VCC Range (V)
Speed (ns)
Operating ICC, (mA)
f = fmax
Standby, ISB2 (µA)
Typ[4]
Max
Typ[4]
Max
1.65 V–2.2 V
55
15
20
3.5
10
2.2 V–3.6 V
45
15
20
3.5
8.7
4.5 V–5.5 V
Optional ERR
CY62146G(E)SL[5] pin
2.2 V–3.6 V and
4.5 V–5.5 V
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
2. This device does not support automatic write-back on error detection.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
5. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
Cypress Semiconductor Corporation
Document Number: 001-95420 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2017
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Logic Block Diagram – CY62146G/CY62146GSL
MEMORY
ARRAY
ECC DECODER
INPUT BUFFER
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
OE
CE2
CE1
BLE
Logic Block Diagram – CY62146GE/CY62146GESL
ECC DECODER
MEMORY
ARRAY
INPUT BUFFER
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
ERR
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
OE
BLE
Document Number: 001-95420 Rev. *E
CE2
CE1
Page 2 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Contents
Pin Configuration – CY62146G/CY62146GSL ................ 4
Pin Configuration – CY62146GE ..................................... 6
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Data Retention Characteristics ..................................... 11
Data Retention Waveform .............................................. 11
AC Switching Characteristics ....................................... 12
Switching Waveforms .................................................... 13
Truth Table – CY62146G/CY62146GE/
CY62146GSL/CY62146GESL ......................................... 17
ERR Output – CY62146GE/CY62146GESL ................... 17
Document Number: 001-95420 Rev. *E
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 3 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Pin Configuration – CY62146G/CY62146GSL
Figure 1. 48-ball VFBGA pinout (Dual Chip Enable without ERR) – CY62146G/CY62146GSL [6]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Figure 2. 48-ball VFBGA pinout (Single Chip Enable without ERR) – CY62146G/CY62146GSL [6]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Note
6. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-95420 Rev. *E
Page 4 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Pin Configuration – CY62146G/CY62146GSL (continued)
Figure 3. 44-pin TSOP II pinout (Single Chip Enable without ERR) – CY62146G/CY62146GSL [7]
A4
A3
A2
A1
A0
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44- TSOP-II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Note
7. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-95420 Rev. *E
Page 5 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Pin Configuration – CY62146GE
Figure 4. 48-ball VFBGA pinout (Single Chip Enable with ERR) – CY62146GE [8, 9]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
ERR
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Figure 5. 48-ball VFBGA pinout (Dual Chip Enable with ERR) – CY62146GE [8, 9]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
ERR
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes
8. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
9. ERR is an output pin.
Document Number: 001-95420 Rev. *E
Page 6 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Pin Configuration – CY62146GE (continued)
Figure 6. 44-pin TSOP II pinout (Single Chip Enable with ERR) – CY62146GE /CY62146GESL[10, 11]
A4
A3
A2
A1
A0
/CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44- TSOP-II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
ERR
A8
A9
A10
A11
A12
Notes
10. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
11. ERR is an output pin.
Document Number: 001-95420 Rev. *E
Page 7 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
DC input voltage[12] ............................ –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential[12] ......................... –0.5 V to VCC + 0.5 V
Output current into outputs (in low state) .................... 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
DC voltage applied to outputs
in HI-Z state[12] .................................... –0.5 V to VCC + 0.5 V
Grade
Industrial
[13]
Ambient Temperature
VCC
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
45/55 ns
Test Conditions
Min
Typ
Max
Output HIGH 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
1.4
–
–
2
–
–
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA
VOL
VCC –
VIL
V
–
–
Output LOW 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
voltage
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
–
–
0.2
–
–
0.4
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
0.4
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA
VIH
0.5[14]
Input HIGH
voltage
Input LOW
voltage
1.65 V to 2.2 V –
–
–
0.4
1.4
–
VCC + 0.2[12]
0.3[12]
2.2 V to 2.7 V –
1.8
–
VCC +
2.7 V to 3.6 V –
2
–
VCC + 0.3[12]
4.5 V to 5.5 V –
2.2
1.65 V to 2.2 V –
–
VCC + 0.5[12]
[12]
–
0.4
[12]
–
0.6
[12]
–
0.8
–0.2
2.2 V to 2.7 V –
–0.3
2.7 V to 3.6 V –
–0.3
[12]
Unit
V
V
V
–0.5
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC,
Output disabled
–1
–
+1
A
ICC
VCC operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
–
15
20
mA
f = 18.18 MHz
(55 ns)
–
15
20
mA
f = 1 MHz
–
–
6
mA
4.5 V to 5.5 V –
Notes
12. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
13. Wide voltage range part supports VCC range of 2.2 V–3.6 V and 4.5 V–5.5 V. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V–4.5 V.
14. This parameter is guaranteed by design and not tested.
Document Number: 001-95420 Rev. *E
Page 8 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
ISB1[15]
Description
Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
ISB2
[15]
Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Min
Typ
Max
–
3.5
8.7
–
–
10
25 °C [16]
–
3.5
3.7
40 °C
[16]
–
–
4.8
70 °C
[16]
–
–
7
CE1 > VCC – 0.2 V or CE2 < 0.2 V
Unit
A
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
CE1 > VCC – 0.2V or
CE2 < 0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V,
85 °C
–
–
8.7
25 °C
[16]
–
3.5
4.3
40 °C
[16]
–
–
5
VIN > VCC – 0.2 V or VIN < 0.2 V, 70 °C
[16]
–
–
7.5
–
–
10
f = 0, Max VCC
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
45/55 ns
Test Conditions
CE1 > VCC – 0.2V or CE2 < 0.2 V
f = 0, Max VCC
85 °C
A
Notes
15. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
16. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-95420 Rev. *E
Page 9 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Capacitance
Parameter [17]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [17]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.35
68.85
°C/W
14.74
15.97
°C/W
AC Test Loads and Waveforms
Figure 7. AC Test Loads and Waveforms [18]
R1
VCC
OUTPUT
VHIGH
GND
R2
30 pF*
*Including
jig and scope
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
Notes
17. Tested initially and after any design or process changes that may affect these parameters.
18. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95420 Rev. *E
Page 10 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
Description
VDR
VCC for data retention
ICCDR[20, 21]
Data retention current
Conditions
VCC = 1.2 V,
Min
Typ [19]
Max
Unit
1
–
–
V
13
A
–
CE1 > VCC 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR
[22, 23]
tR[23]
Chip deselect to data retention
time
Operation recovery time
0
–
–
ns
45/55
–
–
ns
Data Retention Waveform
Figure 8. Data Retention Waveform
V CC
V C C ( m in )
tCDR
D A T A R E T E N T I O N M O D E
V D R = 1 . 0 V
V C C ( m in )
tR
C E 1
CE2
Notes
19. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
20. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
21. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
22. These parameters are guaranteed by design.
23. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95420 Rev. *E
Page 11 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
AC Switching Characteristics
Parameter [24]
45 ns
Description
55 ns
Unit
Min
Max
Min
Max
45
–
55
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid / Address to ERR valid
–
45
–
55
ns
tOHA
Data hold from address change / ERR hold from
address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
–
45
–
55
ns
tDOE
OE LOW to data valid / OE LOW to ERR valid
–
22
–
25
ns
5
–
5
–
ns
–
18
–
18
ns
10
–
10
–
ns
–
18
–
18
ns
tLZOE
OE LOW to low impedance
tHZOE
OE HIGH to HI-Z [25, 26, 27]
tLZCE
tHZCE
[25, 26]
CE1 LOW and CE2 HIGH to low impedance
CE1 HIGH and CE2 LOW to HI-Z
[25, 26]
[25, 26, 27]
[26]
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down [26]
–
45
–
55
ns
tDBE
BLE / BHE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
–
18
–
18
ns
tLZBE
BLE / BHE LOW to low impedance
tHZBE
[25, 26, 27]
BLE / BHE HIGH to HI-Z
[25, 26]
Write Cycle [28, 29]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
45
–
ns
tAW
Address setup to write end
35
–
45
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE / BHE LOW to write end
35
–
45
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to HI-Z
[25, 26, 27]
WE HIGH to low impedance
[25, 26]
Notes
24. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
25. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
26. These parameters are guaranteed by design.
27. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
28. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
29. The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-95420 Rev. *E
Page 12 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY62146G (Address Transition Controlled) [30, 31]
tRC
ADDRESS
tAA
t OHA
DATA I / O
PREVIOUS DATA OUT
VALID
DATA OUT VALID
Figure 10. Read Cycle No. 1 of CY62146GE (Address Transition Controlled) [30, 31]
t RC
ADDRESS
tAA
t OHA
DATA I
/O
PREVIOUS DATA OUT VALID
DATA OUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
30. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
31. WE is HIGH for Read cycle.
Document Number: 001-95420 Rev. *E
Page 13 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Switching Waveforms (continued)
Figure 11. Read Cycle No. 2 (OE Controlled) [32, 33, 34]
A D D R ES S
tR C
CE
t PD
t H Z CE
tACE
OE
t HZOE
t DO E
t LZ O E
BH E/
B LE
t DB E
t LZ B E
D A TA I / O
t H Z BE
H IG H IM PE D A N C E
H IG H
IM P ED AN C E
D ATA O U T V ALID
t LZ C E
tP U
V CC
SU PP LY
CURRENT
IS B
Figure 12. Write Cycle No. 1 (WE Controlled) [33, 35, 36]
tWC
ADDRESS
t SCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
t PWE
WE
t HZWE
DATA I/O
tSD
t LZWE
tHD
DATA IN VALID
Notes
32. WE is HIGH for Read cycle.
33. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
34. Address valid prior to or coincident with CE LOW transition.
35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
36. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-95420 Rev. *E
Page 14 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Switching Waveforms (continued)
Figure 13. Write Cycle No. 2 (CE Controlled) [37, 38, 39]
tW C
ADDRESS
tS A
tSCE
CE
tA W
tH A
t PW E
WE
tB W
BHE /
BLE
OE
t HZO E
tH D
tS D
DATA I /O
D A T A IN V A L ID
Figure 14. Write Cycle No. 3 (WE Controlled, OE LOW) [37, 38, 39, 40]
t WC
ADDRESS
t SCE
CE
tBW
BHE /
BLE
tSA
tAW
tHA
t PWE
WE
t LZW E
t HZW E
DATA I /O
tSD
tHD
DATA IN VALID
Notes
37. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
39. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
40. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95420 Rev. *E
Page 15 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Switching Waveforms (continued)
Figure 15. Write Cycle No. 4 (BHE/BLE Controlled) [41, 42, 43]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
tLZWE
DATAIN VALID
Notes
41. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
42. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
43. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-95420 Rev. *E
Page 16 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Truth Table – CY62146G/CY62146GE/CY62146GSL/CY62146GESL
CE1
WE
OE
BHE
BLE
[44]
Mode
Power
X
X
X
X
X[44]
HI-Z
Deselect/Power-down
Standby (ISB)
L
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
HI-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
X
X
HI-Z
Output disabled
Active (ICC)
L
H
H
X
H
H
HI-Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
HI-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
H
CE2
X
Inputs/Outputs
ERR Output – CY62146GE/CY62146GESL
Output[45]
Mode
0
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
HI-Z
Device deselected/outputs disabled/Write operation
Notes
44. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
45. ERR is an output pin. If not used, this pin should be left floating.
Document Number: 001-95420 Rev. *E
Page 17 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
2.2 V–3.6 V CY62146G30-45BVXI
Package
Diagram
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR
CY62146G30-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR, Tape and Reel
CY62146GE30-45BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable with
ERR
CY62146GE30-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable with
ERR, Tape and Reel
CY62146GE30-45ZSXI
51-85087 44-pin TSOP II with ERR
CY62146GE30-45ZSX
51-85087 44-pin TSOP II with ERR, Tape and Reel
CY62146G30-45ZSXI
51-85087 44-pin TSOP II without ERR
CY62146G30-45ZSXIT
51-85087 44-pin TSOP II without ERR, Tape and Reel
4.5 V–5.5 V CY62146GE-45ZSXI
Operating
Range
Package Type
Industrial
51-85087 44-pin TSOP II with ERR
CY62146GE-45ZSXIT
51-85087 44-pin TSOP II with ERR, Tape and Reel
CY62146G-45ZSXI
51-85087 44-pin TSOP II without ERR
CY62146G-45ZSXIT
51-85087 44-pin TSOP II without ERR, Tape and Reel
Ordering Code Definitions
CY 621
4
6
G
X
XX - 45
XX X X
Temperature Grade: X = I
I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA (Single Chip enable)
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: XX = 30 or blank
30 = 3 V typ; no character = 5 V typ
X = blank or E
blank = without ERR output;
E = with ERR output, Single-bit error correction indicator
Process Technology: G = 65 nm
Bus width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-95420 Rev. *E
Page 18 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Package Diagrams
Figure 16. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Figure 17. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-95420 Rev. *E
Page 19 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
VFBGA
Very Fine-Pitch Ball Grid Array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-95420 Rev. *E
Symbol
Unit of Measure
Page 20 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Document History Page
Document Title: CY62146G/CY62146GE/CY62146GSL/CY62146GESL MoBL®, 4-Mbit (256K words × 16 bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 001-95420
Rev.
ECN No.
Orig. of
Change
*B
5023868
VINI
11/25/2015 Changed status from Preliminary to Final.
*C
5080447
NILE
01/11/2016 Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*D
5430481
NILE
09/08/2016 Updated Maximum Ratings:
Updated Note 12 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to Operating Range “2.7 V to 3.6 V” and Test Condition
“VCC = Min, IOH = –1.0 mA”.
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E
5708694
AESATMP8
Document Number: 001-95420 Rev. *E
Submission
Date
Description of Change
04/26/2017 Updated logo and Copyright.
Page 21 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95420 Rev. *E
Revised April 26, 2017
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 22 of 22
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