CY62146GN MoBL®
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
■
Wide voltage range: 2.20 V to 3.60 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■
Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in a 44-pin TSOP II and 48-ball VFBGA Packages
The CY62146GN is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 001-95417 Rev. *E
•
BHE
WE
CE
OE
BLE
A17
A16
A15
A13
A14
A12
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 15, 2017
CY62146GN MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-95417 Rev. *E
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY62146GN MoBL®
Pin Configurations
Figure 1. 44-pin TSOP II Pinout [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 2. 48-ball VFBGA Pinout [1]
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
Min
CY62146GN30
CY62146GN
Industrial
Typ[2]
Speed
(ns)
Max
2.2
3.0
3.6
45
4.5
5.0
5.5
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
3.5
6
15
20
3.5
8.7
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-95417 Rev. *E
Page 3 of 16
CY62146GN MoBL®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Operating Range
Supply voltage
to ground potential ........................... –0.3 V to + VCC + 0.5 V
DC voltage applied to outputs
in High-Z state[3, 4] ........................... –0.3 V to + VCC + 0.5 V
DC input
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up Current .................................................... >200 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
voltage[3, 4]
Output current into outputs (LOW) ............................. 20 mA
Device
Range
Ambient
Temperature
VCC[5]
CY62146GN30
Industrial
–40 °C to +85 °C
2.2 V to 3.6 V,
4.5 V to 5.5 V
........................ –0.3 V to + VCC + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH[4]
VIL[3]
Description
Output high
voltage
Output low
voltage
Input high
voltage
Input LOW
Voltage
Test Conditions
45 ns
Min
Typ[6]
Max
2.2 V to 2.7 V
VCC = Min, IOH = –0.1 mA
2
–
–
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC – 0.5[7]
–
–
2.2 V to 2.7 V
VCC = Min, IOL = 0.1 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
2.2 V to 2.7 V
–
1.8
–
VCC + 0.3
2.7 V to 3.6 V
–
2.0
–
VCC + 0.3
4.5 V to 5.5 V
–
2.2
–
VCC + 0.5
2.2 V to 2.7 V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
–0.3
–
0.8
4.5 V to 5.5 V
–
–0.5
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
mA
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
mA
ICC
VCC operating supply current
f = fmax = 1/tRC
–
15
20
–
3.5
6
ISB1
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
Automatic CE power down current – f = fmax (Address and data only),
CMOS inputs
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–
3.5
8.7
A
ISB2[8]
Automatic CE power down current – CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
CMOS inputs
f = 0, VCC = 3.60 V
–
3.5
8.7
A
f = 1 MHz
VCC = VCC(max),
IOUT = 0 mA
CMOS levels
mA
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 2.0 V for pulse durations less than 20 ns.
5. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. This parameter is guaranteed by design and not tested.
8. Chip enable (CE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95417 Rev. *E
Page 4 of 16
CY62146GN MoBL®
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Parameter[9]
Description
Test Conditions
48-ball VFBGA
TSOP II
Unit
31.35
68.85
C/W
14.74
15.97
C/W
Thermal resistance Still air, soldered on a
(junction to ambient) 3 × 4.5 inch,
Thermal resistance four-layer printed
circuit board
(junction to case)
JA
JC
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms[10]
R1
VCC
All Input Pulses
VCC
Output
90%
10%
30 pF
GND
Rise Time = 1 V/ns
R2
Including
JIG and
Scope
90%
10%
Fall Time = 1 V/ns
Equivalent to: Thevenin Equivalent
Output
Parameters
2.50 V
R1
R2
RTH
V
3.0 V
Unit
16667
1103
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95417 Rev. *E
Page 5 of 16
CY62146GN MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
VCC for data retention
VCC = 1.2 V, CE > VCC – 0.2 V,
Min
Typ
Max
Unit
1.0
–
–
V
–
–
13
A
ICCDR[11, 12]
Data retention current
tCDR[13]
Chip deselect to data retention
time
–
0
–
–
ns
tR[14]
Operation recovery time
–
45
–
–
ns
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.0 V
tCDR
VCC(min)
tR
CE
Notes
11. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95417 Rev. *E
Page 6 of 16
CY62146GN MoBL®
Switching Characteristics
Over the Operating Range
Parameter[15, 16]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
Low-Z[17]
5
–
ns
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[17, 18]
tLZCE
tHZCE
–
18
ns
CE LOW to
Low-Z[17]
10
–
ns
CE HIGH to
High-Z[17, 18]
–
18
ns
–
ns
tPU
CE LOW to power up
0
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE / BHE LOW to data valid
–
22
ns
BLE / BHE LOW to
Low-Z[17]
5
–
ns
BLE / BHE HIGH to
High-Z[17, 18]
–
18
ns
tLZBE
tHZBE
Write
Cycle[19, 20]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
Address setup to write end
35
–
ns
tAW
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
–
ns
tSD
BLE / BHE LOW to write end
Data setup to write end
35
25
–
ns
tHD
Data hold from write end
tBW
tHZWE
tLZWE
0
–
ns
WE LOW to
High-Z[17, 18]
–
18
ns
WE HIGH to
Low-Z[17]
10
–
ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
16. These parameters are guaranteed by design.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
20. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95417 Rev. *E
Page 7 of 16
CY62146GN MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled)[21, 22]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA I/O
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE.
Document Number: 001-95417 Rev. *E
Page 8 of 16
CY62146GN MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled)[24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 27
tHD
DATAIN
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled)[24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95417 Rev. *E
Page 9 of 16
CY62146GN MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[28, 29]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 30
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 30
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
30. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95417 Rev. *E
Page 10 of 16
CY62146GN MoBL®
Truth Table
CE [31]
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/power-down
Standby (ISB)
L
X
X
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
Read
Active (ICC)
Inputs/Outputs
Mode
Power
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
X
X
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
Write
Active (ICC)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Note
31. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-95417 Rev. *E
Page 11 of 16
CY62146GN MoBL®
Ordering Information
Speed Voltage
(ns) Range (V)
2.2 V–3.6 V
45
4.5 V–5.5 V
Package
Diagram
Ordering Code
Package Type (Pb-free)
CY62146GN30-45ZSXI
51-85087
44-pin TSOP II
CY62146GN30-45ZSXIT
51-85087
44-pin TSOP II, Tape & Reel
CY62146GN30-45BVXI
51-85150
48-ball VFBGA (6 × 8 × 1 mm)
CY62146GN30-45BVXIT
51-85150
48-ball VFBGA (6 × 8 × 1 mm), Tape & Reel
CY62146GN-45ZSXI
51-85087
44-pin TSOP II
CY62146GN-45ZSXIT
51-85087
44-pin TSOP II, Tape & Reel
Operating
Range
Industrial
Ordering Code Definitions
CY 621 4
6 GN 30 - 45 XX
X
X
X
X: T = Tape and Reel; Blank = Bulk
Temperature Grade: X = I; I = Industrial
Pb-free
Package Type: XX = ZS or BV
ZS = TSOP II; BV = 48-Ball VFBGA
Speed Grade: 45 ns
Voltage Range: 30 = 3 V typical, No Character = 5 V typical
Process Technology: GN = 65 nm Technology
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-95417 Rev. *E
Page 12 of 16
CY62146GN MoBL®
Package Diagrams
Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Figure 12. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-95417 Rev. *E
Page 13 of 16
CY62146GN MoBL®
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
Degrees Celsius
CMOS
complementary metal oxide semiconductor
MHz
megahertz
CE
chip enable
A
microamperes
I/O
input/output
mA
milliamperes
OE
output enable
ns
nanoseconds
SRAM
static random access memory
ohms
TSOP
thin small outline package
pF
picofarads
VFBGA
very fine-pitch ball grid array
V
volts
WE
write enable
W
watts
Document Number: 001-95417 Rev. *E
Symbol
Unit of Measure
Page 14 of 16
CY62146GN MoBL®
Document History Page
Document Title: CY62146GN MoBL®, 4-Mbit (256K × 16) Static RAM
Document Number: 001-95417
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
5048897
NILE
12/14/2015
New data sheet.
01/05/2016
Added “4.5 V to 5.5 V” voltage range related information in all instances across
the document.
Updated Ordering Information:
Updated part numbers.
*A
5072822
NILE
Description of Change
*B
5092237
NILE
01/21/2016
Added 48-ball VFBGA package related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85150 *H (Figure 12).
*C
5142534
NILE
02/18/2016
Updated Ordering Code Definitions under Ordering Information (Replaced
“GN = 90 nm” with “GN = 65 nm Technology”).
Updated to new template.
*D
5555156
NILE
12/15/2016
Updated Ordering Information: Updated part numbers.
Updated Electrical Characteristics:
Enhance VIH for 2.2V - 2.7V operating range from 2.0V to 1.8V.
Enhance VOH for 2.7V - 3.6V operating range from 2.2V to 2.4V.
Updated Notes 3 and 4.
Updated Thermal Resistance.
Updated Sales Support, Copyright and Disclaimer.
*E
5995870
AESATMP9
12/15/2017
Updated logo and copyright.
Document Number: 001-95417 Rev. *E
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CY62146GN MoBL®
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© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
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expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95417 Rev. *E
Revised December 15, 2017
Page 16 of 16
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