CY621472E30 MoBL® Automotive
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE1
HIGH or CE2 LOW or both BLE and BHE are HIGH). The input
and output pins (I/O0 through I/O15) are placed in a
high-impedance state when:
Very high speed: 45 ns
Temperature range
❐ Automotive-A: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Automotive-A)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■
■
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP)
II package
■
Byte power down feature
■
Deselected (CE1 HIGH or CE2 LOW)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE1 LOW and CE2 HIGH and WE
LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from the I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A17). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
the memory appears on I/O8 to I/O15. See the Truth Table on
page 11 for a complete description of read and write modes.
Functional Description
The CY621472E30 is a high-performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
Logic Block Diagram
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A17
A15
A16
A13
A14
A12
BHE
BLE
CIRCUIT
A11
CE
POWER DOWN
BHE
WE
CE1
CE2
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-89978 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 7, 2016
CY621472E30 MoBL® Automotive
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Load and Waveforms ......................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-89978 Rev. *B
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC®Solutions ....................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY621472E30 MoBL® Automotive
Product Portfolio
Power Dissipation
Product
CY621472E30LL
Range
Automotive-A
VCC Range (V)
Min
Typ [1]
Max
2.2
3.0
3.6
Speed
(ns)
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
2
2.5
15
20
1
7
Pin Configuration
Figure 1. 44-pin TSOP II pinout
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
CE2
A8
A9
A10
A11
A12
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-89978 Rev. *B
Page 3 of 16
CY621472E30 MoBL® Automotive
DC input voltage [2, 3] ......... –0.3 V to 3.9 V (VCCmax + 0.3 V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Supply voltage
to ground potential ........... –0.3 V to +3.9 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High Z State [2, 3] ............ –0.3 V to 3.9 V (VCCmax + 0.3 V)
Device
Range
Ambient
Temperature
VCC[4]
CY621472E30LL Automotive-A –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the operating range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
45 ns
Unit
Min
Typ[5]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC = 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
–
15
20
mA
–
2
2.5
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
ISB1 [6]
Automatic CE power-down
current — CMOS inputs
CE1 > VCC – 0.2 V, CE2 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–
1
7
A
ISB2 [6]
Automatic CE power-down
current — CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
7
A
Notes
2. VIL (min) = –2.0 V for pulse durations less than 20 ns.
3. VIH (max) = VCC + 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a minimum of 100-s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ), TA = 25 °C.
6. Chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-89978 Rev. *B
Page 4 of 16
CY621472E30 MoBL® Automotive
Capacitance
Parameter [7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC (typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
44-pin TSOP II Unit
Package
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
55.52
C/W
16.03
C/W
AC Test Load and Waveforms
Figure 2. AC Test Load and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
R2
INCLUDING
JIG AND
SCOPE
10%
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
Parameters
ALL INPUT PULSES
90%
90%
10%
RTH
2.50 V
VTH
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-89978 Rev. *B
Page 5 of 16
CY621472E30 MoBL® Automotive
Data Retention Characteristics
Over the operating range
Parameter
Description
Conditions
Min
Typ [8]
Max
Unit
1.5
–
–
V
–
0.8
7
A
VDR
VCC for data retention
ICCDR[9]
Data retention current
tCDR[10]
Chip deselect to data retention
time
0
–
–
ns
tR[11]
Operation recovery time
45
–
–
ns
VCC = 1.5 V,
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform [12, 13]
DATA RETENTION MODE
VCC
CE or
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
BHE.BLE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
12. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-89978 Rev. *B
Page 6 of 16
CY621472E30 MoBL® Automotive
Switching Characteristics
Over the Operating Range
Parameter [14]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW/CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[15]
5
–
ns
–
18
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to
High-Z[15, 16]
Low-Z[15]
tLZCE
CE1 LOW/CE2 HIGH to
10
–
ns
tHZCE
CE1 HIGH/CE2 LOW to High-Z[15, 16]
–
18
ns
tPU
CE1 LOW/CE2 HIGH to Power-up
0
–
ns
tPD
CE1 HIGH/CE2 LOW to Power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
tLZBE
BLE/BHE LOW to Low-Z[15, 17]
5
–
ns
–
18
ns
tHZBE
Write
BLE/BHE HIGH to
High-Z[15, 16]
Cycle[18]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High-Z[15, 16]
–
18
ns
10
–
ns
tLZWE
[15]
WE HIGH to Low-Z
Notes
14. Test conditions for all parameters other than tristate parameters assume a signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. If both byte enables are together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 001-89978 Rev. *B
Page 7 of 16
CY621472E30 MoBL® Automotive
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [19, 20]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [20, 21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
ICC
50%
ISB
Notes
19. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
20. WE is HIGH for read cycle.
21. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
22. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-89978 Rev. *B
Page 8 of 16
CY621472E30 MoBL® Automotive
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 27
tHD
DATAIN
tHZOE
Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
23. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
25. Data I/O is high-impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-89978 Rev. *B
Page 9 of 16
CY621472E30 MoBL® Automotive
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [28, 29]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 30
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [28, 29]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 30
tSD
tHD
DATAIN
tLZWE
Notes
28. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
29. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-89978 Rev. *B
Page 10 of 16
CY621472E30 MoBL® Automotive
Truth Table
CE1
H
CE2
I/Os
Mode
Power
WE
OE
BHE
BLE
[31]
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
X
X[31]
L
X
X
X
X
High-Z
Deselect/Power-down
Standby (ISB)
[31]
X
X
H
H
High-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
H
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
[31]
X
X
Note
31. The ‘X’ (Don’t care) state for the chip enables (CE1 and CE2) in the Truth Table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-89978 Rev. *B
Page 11 of 16
CY621472E30 MoBL® Automotive
Ordering Information
Speed
(ns)
45
Ordering Code
CY621472E30LL-45ZSXA
Package
Diagram
Package Type
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Automotive-A
Ordering Code Definitions
CY 621 4
7 2
E 30
LL - 45
ZS
X
A
Temperature Range: A = Automotive-A
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Voltage Range: 3 V Typical
Process Technology: 90 nm
Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-89978 Rev. *B
Page 12 of 16
CY621472E30 MoBL® Automotive
Package Diagram
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-89978 Rev. *B
Page 13 of 16
CY621472E30 MoBL® Automotive
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
OE
Output Enable
MHz
megahertz
SRAM
Static Random Access Memory
A
microampere
TSOP
Thin Small Outline Package
s
microsecond
WE
Write Enable
mA
milliampere
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-89978 Rev. *B
Symbol
Unit of Measure
Page 14 of 16
CY621472E30 MoBL® Automotive
Document History Page
Document Title: CY621472E30 MoBL® Automotive, 4-Mbit (256K × 16) Static RAM
Document Number: 001-89978
Rev.
ECN No.
Orig. of
Change
Submission
Date
*A
4316520
VINI
03/21/2014
Changed status from Preliminary to Final.
*B
5545167
VINI
12/07/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter corresponding to 44-pin TSOP II Package
from 77 C/W to 55.52 C/W.
Changed value of JC parameter corresponding to 44-pin TSOP II Package
from 13 C/W to 16.03 C/W.
Updated to new template.
Completing Sunset Review.
Document Number: 001-89978 Rev. *B
Description of Change
Page 15 of 16
CY621472E30 MoBL® Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2013-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
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Document Number: 001-89978 Rev. *B
Revised December 7, 2016
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor Corporation.
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