CY62147CV30LL-55BAI

47V CY62147CV25/30/33 MoBL™ 256K x 16 Static RAM Features cantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). • High Speed — 55 ns and 70 ns availability • Voltage range: — CY62147CV25: 2.2V–2.7V — CY62147CV30: 2.7V–3.3V — CY62147CV33: 3.0V–3.6V • Pin Compatible with CY62147V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). — Typical active current: 5.5 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description The CY62147CV25/30/33 are high-performance CMOS static RAMs organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that signifi- The CY62147CV25/30/33 are available in a 48-ball FBGA package. Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array 2048 x 2048 I/O0 – I/O7 I/O8 – I/O15 A17 BHE WE CE OE BLE CE Power -Down Circuit Cypress Semiconductor Corporation Document #: 38-05202 Rev. *A A13 A14 A15 A16 A11 A12 COLUMN DECODER BHE BLE • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 24, 2002 CY62147CV25/30/33 MoBL™ Pin Configuration[1, 2] FBGA (Top View) 4 3 5 1 2 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 6 NC H Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Device Range Ambient Temperature VCC Supply Voltage to Ground Potential ...–0.5V to Vccmax + 0.5V CY62147CV25 Industrial –40°C to +85°C 2.2V to 2.7V DC Voltage Applied to Outputs in High Z State[3] ....................................–0.5V to VCC + 0.3V CY62147CV30 2.7V to 3.3V CY62147CV33 3.0V to 3.6V DC Input Voltage[3] .................................-0.5V to VCC + 0.3V Output Current into Outputs (LOW) .............................20 mA Product Portfolio Power Dissipation (Industrial) Operating, ICC VCC Range Product VCC(min.) VCC(typ.) [4] f = 1 MHz 55 ns 1.5 mA 3 mA 70 ns 1.5 mA 3 mA 55 ns 1.5 mA 3 mA 70 ns 1.5 mA 3 mA 55 ns 1.5 mA 3 mA 70 ns 1.5 mA 3 mA 2.7V CY62147CV30 2.7V 3.0V 3.3V 3.3V 7 mA Typ. 2.5V 3.0V Typ. Speed 2.2V CY62147CV33 Max. VCC(max.) CY62147CV25 3.6V f = fmax [4] [4] Standby (ISB2) Max. Typ.[4] Max. 15 mA 5 µA 15 µA 7 µA 15 µA 8 µA 20 µA 5.5 mA 12 mA 7 mA 15 mA 5.5 mA 12 mA 7 mA 15 mA 5.5 mA 12 mA Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05202 Rev. *A Page 2 of 14 CY62147CV25/30/33 MoBL™ Electrical Characteristics Over the Operating Range CY62147CV25-55 Parameter Description Test Conditions Min. Typ. [4] Max. VOH Output HIGH Voltage IOH = –0.1 mA VCC = 2.2V VOL Output LOW Voltage IOL = 0.1 mA VCC = 2.2V VIH Input HIGH Voltage 1.8 VCC + 0.3V VIL Input LOW Voltage –0.3 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 2.7V ISB2 f = 1 MHz 2.0 Description Typ.[4] Max. Unit V 0.4 0.4 V 1.8 VCC + 0.3V V 0.6 –0.3 0.6 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA mA VCC = 2.7V IOUT = 0 mA CMOS Levels Test Conditions Min. 2.0 7 15 5.5 12 1.5 3 1.5 3 5 15 5 15 CY62147CV30-55 Parameter CY62147CV25-70 Min. Typ. [4] Max. CY62147CV30-70 Min. Typ.[4] Max. Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC mA ICC ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.3V ISB2 Document #: 38-05202 Rev. *A f = 1 MHz 2.4 Unit VOH VCC = 3.3V IOUT = 0 mA CMOS Levels 2.4 µA V 0.4 7 15 5.5 12 1.5 3 1.5 3 7 15 7 15 µA Page 3 of 14 CY62147CV25/30/33 MoBL™ Electrical Characteristics Over the Operating Range (continued) CY62147CV33-55 Parameter Description Test Conditions Min. [4] Typ. Max. Min. Typ.[4] Max. Unit VOH Output HIGH Voltage IOH = –1.0 mA VCC = 3.0V VOL Output LOW Voltage IOL = 2.1 mA VCC = 3.0V 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC mA ICC ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) Automatic CE Power-Down Current— CMOS Inputs CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V ISB2 f = 1 MHz 2.4 CY62147CV33-70 2.4 V 0.4 VCC = 3.6V IOUT = 0 mA CMOS Levels 7 15 5.5 12 1.5 3 1.5 3 8 20 8 20 µA . Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board Thermal Resistance (Junction to Case)[5] Symbol BGA Unit ΘJA 55 °C/W ΘJC 16 °C/W Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05202 Rev. *A Page 4 of 14 CY62147CV25/30/33 MoBL™ AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT 10% GND Rise TIme: 1 V/ns R2 30 pF 90% 10% 90% Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5V 3.0V 3.3V Unit R1 16.6 1.105 1.216 KΩ R2 15.4 1.550 1.374 KΩ RTH 8 0.645 0.645 KΩ VTH 1.20 1.75 1.75 Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions VCC for Data Retention Min. Typ.[4] 1.5 Data Retention Current ICCDR tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time VCC= 1.5V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 3 Max. Unit Vccmax V 10 µA 0 ns tRC ns Data Retention Waveform[7] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE or BHE.BLE Note: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100µs or stable at VCC(min.) >100 µs. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05202 Rev. *A Page 5 of 14 CY62147CV25/30/33 MoBL™ Switching Characteristics Over the Operating Range[8] 55 ns Parameter Description Min 70 ns Max Min Max Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[9] 10 tLZCE CE LOW to Low Z 10 25 5 OE HIGH to High Z 10 [9, 11] tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE BHE / BLE LOW to Data Valid [9] BHE / BLE LOW to Low Z tHZBE BHE / BLE HIGH to High Z[9, 11] ns 35 ns ns 25 20 tLZBE[10] 70 10 0 ns ns 5 20 [9] ns 70 55 [9, 11] tHZOE 70 55 ns ns 25 0 ns ns 55 70 ns 55 70 ns 5 5 20 ns 25 ns [12] WRITE CYCLE tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tBW BHE / BLE Pulse Width 50 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns [9, 11] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[9] 20 5 25 5 ns ns Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05202 Rev. *A Page 6 of 14 CY62147CV25/30/33 MoBL™ Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05202 Rev. *A Page 7 of 14 CY62147CV25/30/33 MoBL™ Switching Waveforms (continued) [12, 16, 17] Write Cycle No. 1 (WE Controlled) tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 18 tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05202 Rev. *A Page 8 of 14 CY62147CV25/30/33 MoBL™ Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tHD tSD DATAI/O NOTE 18 DATAIN VALID tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [17] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 18 Document #: 38-05202 Rev. *A tHD DATAIN VALID Page 9 of 14 CY62147CV25/30/33 MoBL™ Typical DC and AC Parameters (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.) Operating Current vs. Supply Voltage 12.0 10.0 10.0 (f = fmax, 55 ns) 8.0 (f = fmax, 70 ns) 6.0 ICC (mA) 12.0 MoBL 12.0 (f = fmax, 55 ns) 8.0 (f = fmax, 70 ns) 6.0 ICC (mA) MoBL ICC (mA) 14.0 14.0 14.0 10.0 2.0 4.0 2.0 (f = 1 MHz) 0.0 3.3 3.0 3.6 SUPPLY VOLTAGE (V) (f = 1 MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) 0.0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) (f = fmax, 70n s) 6.0 2.0 (f = 1 MHz) (f = fmax, 55 ns) 8.0 4.0 4.0 MoBL 12.0 12.0 12.0 10.0 10.0 10.0 MoBL 8.0 ISB (µA) 8.0 MoBL ISB (µA) ISB (µA) Standby Current vs. Supply Voltage MoBL 8.0 6.0 6.0 6.0 4.0 4.0 4.0 2.0 2.0 2.0 0 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) 0 3.0 2.7 SUPPLY VOLTAGE (V) 3.3 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage MoBL MoBL 60 60 50 50 50 40 40 40 30 30 30 20 20 10 10 0 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) Document #: 38-05202 Rev. *A TAA (ns) 60 TAA (ns) TAA (ns) MoBL 20 10 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.0 3.3 3.6 SUPPLY VOLTAGE (V) Page 10 of 14 CY62147CV25/30/33 MoBL™ Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (ISB) X X X H H High Z Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name 70 CY62147CV25LL-70BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV25LL-70BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62147CV30LL-70BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV30LL-70BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62147CV33LL-70BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV33LL-70BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62147CV25LL-55BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV25LL-55BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62147CV30LL-55BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV30LL-55BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62147CV33LL-55BAI BA48B 48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm) CY62147CV33LL-55BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 55 Document #: 38-05202 Rev. *A Package Type Operating Range Industrial Page 11 of 14 CY62147CV25/30/33 MoBL™ Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B 51-85106-*C Document #: 38-05202 Rev. *A Page 12 of 14 CY62147CV25/30/33 MoBL™ Package Diagrams (continued) 48-Lead VFBGA (6 mm x 8 mm x 1 mm) BV48A 51-85150-** MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05202 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62147CV25/30/33 MoBL™ Document Title: CY62147CV25/30/33 MoBL™ 256K x 16 Static RAM Document Number: 38-05202 REV. ECN NO. Issue Date ** 112394 01/31/02 *A 114216 05/01/02 Document #: 38-05202 Rev. *A Orig. of Change Description of Change GAV Converted from Spec# 38-01123 to 38-05202. Advance Information to Final MGN/GUG Improved Typical & Max Icc values Page 14 of 14