CY62147EV18_10

CY62147EV18 MoBL® 4-Mbit (256K x 16) Static RAM is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), or during an active write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the “Truth Table” on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Features ■ ■ ■ ■ Very high speed: 55 ns Wide voltage range: 1.65 V to 2.25 V Pin compatible with CY62147DV18 Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz Ultra low standby power Easy memory expansion with CE and OE features Automatic power down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in a Pb-free 48-ball very fine ball grid array (VFBGA) package ■ ■ ■ ■ ■ ■ Functional Description The CY62147EV18 is a high performance CMOS static RAM organized as 256 K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER POWER DOWN CIRCUIT CE BHE WE CE OE BLE A11 A12 A13 A15 A14 BLE A16 A17 BHE Cypress Semiconductor Corporation Document #: 38-05441 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 Revised October 06, 2010 • 408-943-2600 [+] Feedback CY62147EV18 MoBL® Contents Features ...............................................................................1 Functional Description .......................................................1 Product Portfolio ................................................................3 Pin Configuration ...............................................................3 Maximum Ratings ...............................................................4 Operating Range .................................................................4 Electrical Characteristics ...................................................4 Capacitance ........................................................................4 Thermal Resistance ............................................................5 Data Retention Characteristics .........................................5 Switching Characteristics ..................................................6 Switching Waveforms ........................................................ 7 Truth Table ........................................................................ 10 Ordering Information ........................................................ 11 Ordering Code Definition ............................................. 11 Package Diagram .............................................................. 12 Acronyms .......................................................................... 13 Document Conventions ................................................... 13 Units of Measure ......................................................... 13 Document History Page ................................................... 14 Sales, Solutions, and Legal Information ........................ 16 Worldwide Sales and Design Support ......................... 16 Products ...................................................................... 16 PSoC Solutions ........................................................... 16 Document #: 38-05441 Rev. *H Page 2 of 16 [+] Feedback CY62147EV18 MoBL® Product Portfolio Power Dissipation Product VCC Range (V) Min CY62147EV18LL 1.65 Typ [1] 1.8 Max 2.25 55 Speed (ns) Typ [1] 2 Operating ICC (mA) f = 1MHz Max 2.5 f = fmax Typ [1] 15 Max 20 Standby ISB2 (A) Typ [1] 1 Max 7 Pin Configuration Figure 1. 48-Ball VFBGA Pinout [2, 3] Top View 1 BLE I/O8 I/O9 2 OE BHE I/O10 3 A0 A3 A5 A17 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H VSS I/O11 VCC I/O12 I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9 Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C 2. NC pins are not connected on the die. 3. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively. Document #: 38-05441 Rev. *H Page 3 of 16 [+] Feedback CY62147EV18 MoBL® Maximum Ratings Exceeding the maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ........................ –0.2 V to + 2.45 V (VCCmax + 0.2 V) DC voltage applied to outputs in High Z state[4, 5] ............. –0.2 V to 2.45 V (VCCmax + 0.2 V) DC input voltage[4, 5] .......... –0.2 V to 2.45 V (VCCmax + 0.2 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage ......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up current ..................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[6] 1.65 V to 2.25 V CY62147EV18LL Industrial –40 °C to +85 °C Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current IOH = –0.1 mA IOL = 0.1 mA VCC =1.65 V to 2.25 V VCC =1.65 V to 2.25 V GND < VI < VCC f = fmax = 1/tRC Test Conditions 55 ns Min 1.4 Typ[7] – – Max – 0.2 VCC+ 0.2 0.4 +1 +1 20 Unit V V V V A A mA 1.4 –0.2 –1 –1 VCC(max) = 2.25 V IOUT = 0 mA CMOS levels VCC(max) = 2.25 V – – – – – 15 Output leakage current GND < VO < VCC, Output Disabled VCC operating supply current f = 1 MHz ISB1[8] – – 2 1 2.5 7 mA A Automatic power down CE > VCC – 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN VCC(max) = 2.25 current – CMOS inputs > VCC – 0.2 V, VIN < 0.2 V) f = fmax (address and data V only), f = 0 (OE, and WE), VCC = VCC (max) Automatic power down CE > VCC  0.2 V or (BHE and BLE) > VCC – 0.2V, VIN VCC(max) = 2.25 V current – CMOS inputs > VCC  0.2 V or VIN < 0.2 V, f = 0, VCC = VCC (max) ISB2[8] – 1 7 A Capacitance Parameter[9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max) =VCC+0.5 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05441 Rev. *H Page 4 of 16 [+] Feedback CY62147EV18 MoBL® Thermal Resistance Parameter[10] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board VFBGA Package 75 10 Unit C / W C / W Figure 2. AC Test Loads and Waveforms R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns VCC OUTPUT Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH 1.80V 13500 10800 6000 0.80 V Unit    V Parameters R1 R2 RTH VTH Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR[12] Description VCC for data retention Data retention current VCC = 1.0 V, CE > VCC – 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Conditions Min 1.0 – Typ[11] – Max – Unit V A 0.5 5 tCDR[10] tR[13] Chip deselect to data retention time Operation recovery time Figure 3. Data Retention Waveform[14] DATA RETENTION MODE VCC CE or BHE.BLE 0 55 – – – – ns ns VCC(min) tCDR VDR > 1.0 V VCC(min) tR Notes 10. Tested initially and after any design or process changes that may affect these parameters 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s 14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document #: 38-05441 Rev. *H Page 5 of 16 [+] Feedback CY62147EV18 MoBL® Switching Characteristics Over the Operating Range Parameter[15,16] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [19] Description 55 ns Min 55 – Max Unit Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to Low Z CE LOW to Low Z [17] [17, 18] – ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 55 – 10 – 55 25 5 – – OE HIGH to High Z CE HIGH to High Z 18 – [17] [17, 18] 10 – 18 – CE LOW to power up CE HIGH to power down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z [17] [17, 18] 0 – – 55 55 – 10 – BLE/BHE HIGH to High Z Write cycle time CE LOW to write end 18 45 35 35 0 0 35 35 25 0 – – – – – – – – – – Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from write end WE LOW to High Z WE HIGH to Low Z [17, 18] [17] 18 – 10 Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “” on page 5 section 16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document #: 38-05441 Rev. *H Page 6 of 16 [+] Feedback CY62147EV18 MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled)[20, 21] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 (OE controlled)[21, 22] ADDRESS tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE Notes: 20. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 21. WE is high for read cycle. 22. Address valid before or similar to CE and BHE, BLE transition low. Document #: 38-05441 Rev. *H Page 7 of 16 [+] Feedback CY62147EV18 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1(WE Controlled) [23,24,25] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA BHE/BLE tBW OE DATA I/O NOTE 26 tHZOE tSD DATAIN tHD Figure 7. Write Cycle No. 2 ( CE Controlled) [23,24,25] tWC ADDRESS tSCE CE tSA WE tAW tPWE tHA BHE/BLE tBW OE tSD DATA I/O NOTE 26 tHZOE Notes: 23. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. 24. Data I/O is high impedance if OE = VIH. 25. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 26. During this period, the I/Os are in output state. Do not apply input signals. tHD DATAIN Document #: 38-05441 Rev. *H Page 8 of 16 [+] Feedback CY62147EV18 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled and OE LOW) [27] tWC ADDRESS tSCE CE BHE/BLE tAW WE tSA tBW tHA tPWE tSD DATA I/O NOTE 28 tHZWE DATAIN tHD tLZWE Figure 9. Write Cycle No. 4 (BHE/BLE Controlled and OE LOW) [27] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tHZWE tHA tBW tPWE tSD DATAIN tLZWE tHD DATA I/O NOTE 28 Notes 27. If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05441 Rev. *H Page 9 of 16 [+] Feedback CY62147EV18 MoBL® Truth Table CE H X[29] L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE BLE X[29] H L H L L H L L H L Inputs or Outputs Mode Deselect or power down Deselect or power down Read Read Read Output disabled Output disabled Output disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) X[29] High-Z H L L H L L H L L H High-Z Data out (I/O0 – I/O15) Data out (I/O0 – I/O7); I/O8 – I/O15 in High-Z Data out (I/O8 – I/O15); I/O0 – I/O7 in High-Z High-Z High-Z High-Z Data in (I/O0 – I/O15) Data in (I/O0 – I/O7); I/O8 – I/O15 in High-Z Data in (I/O8 – I/O15); I/O0 – I/O7 in High-Z Note 29. The ‘X’ (Do not care) state for the Chip enable (CE) and byte enables (BHE and BLE) in the truth table refer to the logic state (either high or low). Intermediate voltage levels on this pin is not permitted. Document #: 38-05441 Rev. *H Page 10 of 16 [+] Feedback CY62147EV18 MoBL® Ordering Information Speed (ns) 55 Ordering Code CY62147EV18LL-55BVXI Package Diagram Package Type Operating Range Industrial 51-85150 48-ball VFBGA (Pb-free) Contact your local Cypress sales representative for availability of other parts. Ordering Code Definition CY 621 4 7 E V18 LL 45/55 XXX X Temperature grade: I = Industrial Package type: BVX: VFBGA (Pb-free) Speed grade Low power Voltage range = 3 V typical E = Process Technology 90 nm Bus width = x16 Density = 16 Mbit 621 = MoBL SRAM family Company ID: CY = Cypress Document #: 38-05441 Rev. *H Page 11 of 16 [+] Feedback CY62147EV18 MoBL® Package Diagram Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150 *F Document #: 38-05441 Rev. *H Page 12 of 16 [+] Feedback CY62147EV18 MoBL® Acronyms Acronym BHE BLE CMOS CE I/O OE SRAM TSOP VFBGA WE Description byte high enable byte low enable complementary metal oxide semiconductor chip enable input/output output enable static random access memory thin small outline package very fine ball grid array write enable Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts Document #: 38-05441 Rev. *H Page 13 of 16 [+] Feedback CY62147EV18 MoBL® Document History Page Document Title: CY62147EV18 MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 38-05441 REV. ** *A ECN NO. Submission Date 201580 247009 01/08/04 See ECN Orig. of Change AJU SYT New Datasheet Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCCMax from 2.20 to 2.25 V Changed VCC stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #15 (tLZBE) from Previous Revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35 ns Speed Bin Removed “L” version of CY62147EV18 Changed ball E3 from DNU to NC Changed ICC(typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC(max) value from 2 mA to 2.5 mA at f = 1 MHz Changed ICC(typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A Extended undershoot limit to –2 V in footnote #5 Changed ICCDR Max from 2.5 A to 3 A Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced Package Name Column with Package Diagram Replaced 45ns speed bin with 55 ns Description of Change *B 414820 See ECN ZSD *C 571786 See ECN VKN Document #: 38-05441 Rev. *H Page 14 of 16 [+] Feedback CY62147EV18 MoBL® Document Title: CY62147EV18 MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 38-05441 REV. *D ECN NO. Submission Date 908120 See ECN Orig. of Change VKN Description of Change Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters Changed tWC specification from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE specification from 18 ns to 20 ns Changed ICCDR specification from 3 A to 5 A *E *F 1045701 1274728 See ECN See ECN VKN VKN/AESA Changed tWC specification from 55 ns to 45 ns Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns Changed tHZWE specification from 20 ns to 18 ns VKN Added Contents Added footnote related to chip enable in Truth Table Updated Package Diagram Added Sales, Solutions, and Legal Information Added Acronyms and Units of Measure Table Updated Package Diagram from *E to *F version. Updated Data Retention Characteristics and Electrical Characteristics table. Updated and converted all tablenotes into footnotes. *G 2944332 06/04/2010 *H 3047228 10/06/2010 RAME Document #: 38-05441 Rev. *H Page 15 of 16 [+] Feedback CY62147EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05441 Rev. *H Revised October 06, 2010 Page 16 of 16 MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback