CY62147G/CY621472G
MoBL® Automotive
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed: 45 ns/55 ns
■
Temperature Ranges
❐ Automotive-A: -40 C to +85 C
❐ Automotive-E: -40 C to +125 C
■
Ultra-low standby power
❐ Typical standby current: 3.5 A
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
■
Embedded ECC for single-bit error correction[1, 2]
■
Wide voltage range: 2.2 V to 3.6 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
Functional Description
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are deasserted (OE, BLE, BHE).
CY62147G/CY621472G is high-performance CMOS low-power
(MoBL) SRAM devices with embedded ECC. Both devices are
offered in single and dual chip enable options and in multiple pin
configurations.
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
The logic block diagrams are on page 2.
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate 2001 V
Latch-up current ..................................................... >140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
to ground potential [5] .......................... –0.3 V to VCC + 0.3 V
DC voltage applied to outputs
in HI-Z state [5] ..................................... –0.3 V to VCC + 0.3 V
Grade
Ambient Temperature
VCC
Automotive-A
–40 C to +85 C
2.2 V to 3.6 V
Automotive-E
–40 C to +125 C
DC Electrical Characteristics
Over the operating range
Parameter
VOH
VOL
VIH
VIL
Description
Test Conditions
45 ns (Automotive-A)
55 ns (Automotive-E)
Min
Typ
Max
Min
Typ
Max
Output
HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2
–
–
2
–
–
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
2.4
–
–
2.4
–
–
Output
LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
–
–
0.4
–
–
0.4
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
0.4
–
–
0.4
Input HIGH 2.2 V to 2.7 V –
voltage
2.7 V to 3.6 V –
1.8
–
VCC + 0.3[5]
2
–
VCC + 0.3[5]
–
+ 0.3[5]
2
–
+ 0.3[5]
Input LOW 2.2 V to 2.7 V –
voltage
2.7 V to 3.6 V –
–0.3[5]
0.6
–0.3[5]
–
0.6
2
[5]
–
VCC
VCC
Unit
V
V
V
V
–0.3
–
0.8
–0.3[5]
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
–5
–
+5
A
IOZ
Output leakage current
GND < VOUT < VCC,
Output disabled
–1
–
+1
–5
–
+5
A
ICC
VCC operating supply
current
Max VCC,
IOUT = 0 mA,
CMOS levels
f = fMAX
–
15
20
–
15
24
mA
f = 1 MHz
–
3.5
6
–
3.5
10
Note
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 001-95424 Rev. *E
Page 6 of 20
CY62147G/CY621472G
MoBL® Automotive
DC Electrical Characteristics (continued)
Over the operating range
Parameter
ISB1[6]
Description
Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Test Conditions
CE1 > VCC – 0.2 V
or
CE2 < 0.2 V,
45 ns (Automotive-A)
55 ns (Automotive-E)
Min
Typ
Max
Min
Typ
Max
–
3.5
8.7
–
–
35
A
–
3.5
8.7
–
–
35
A
Unit
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = fmax (address and data
only),
f = 0 (OE, and WE), Max VCC
ISB2
[6]
Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
CE1 > VCC – 0.2 V
or
CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V
or
VIN < 0.2 V,
f = 0, Max VCC
Note
6. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95424 Rev. *E
Page 7 of 20
CY62147G/CY621472G
MoBL® Automotive
Capacitance
Parameter [7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.17
66.82
°C/W
14.90
15.97
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [8]
R1
VCC
OUTPUT
VHIGH
GND
R2
30 pF*
*Including
jig and sope
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95424 Rev. *E
Page 8 of 20
CY62147G/CY621472G
MoBL® Automotive
Data Retention Characteristics
Over the operating range
Parameter
Description
VDR
VCC for data retention
ICCDR[10, 11]
Data retention current
Conditions
Vcc = 1.2 V,
(Automotive-A)
Min
Typ
[9]
(Automotive-E)
Max
Min
Typ[9]
Max
Unit
1
–
–
1
–
–
V
–
–
13
–
–
50
A
CE1 > VCC 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[12]
Chip deselect to data
retention time
0
–
–
0
–
–
ns
tR[12, 13]
Operation recovery time
45
–
–
55
–
–
ns
Data Retention Waveform
Figure 5. Data Retention Waveform [14]
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
C E 1 o r
B H E . B L E
CE2
Notes
9. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. ICCDR is guaranteed only after the device is first powered up to VCC(min) and then brought down to VDR.
12. These parameters are guaranteed by design.
13. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-95424 Rev. *E
Page 9 of 20
CY62147G/CY621472G
MoBL® Automotive
AC Switching Characteristics
Parameter [15]
Description
45 ns
55 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
tLZOE
OE LOW to Low impedance
[16, 17]
HI-Z[16, 17, 18]
tHZOE
OE HIGH to
tLZCE
CE1 LOW and CE2 HIGH to Low impedance[16, 17]
–
18
–
18
ns
10
–
10
–
ns
CE1 HIGH and CE2 LOW to
HI-Z[16, 17, 18]
–
18
–
18
ns
CE1 LOW and CE2 HIGH to
power-up[17]
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to
power-down[17]
–
45
–
55
ns
tDBE
BLE / BHE LOW to data valid
–
45
–
55
ns
5
–
5
–
ns
–
18
–
18
ns
tHZCE
tPU
tLZBE
tHZBE
Write Cycle
BLE / BHE LOW to Low
BLE / BHE HIGH to
impedance[16, 17]
HI-Z[16, 17, 18]
[19, 20]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
40
–
ns
tAW
Address setup to write end
35
–
40
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE / BHE LOW to write end
35
–
45
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to
HI-Z[16, 17, 18]
WE HIGH to Low
impedance[16, 17]
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. These parameters are guaranteed by design.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
20. The minimum pulse width in Write Cycle No 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-95424 Rev. *E
Page 10 of 20
CY62147G/CY621472G
MoBL® Automotive
Switching Waveforms
Figure 6. Read Cycle No. 1 of CY62147G/CY621472G (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
t OHA
PREVIOUS DATA OUT
VALID
DATA I / O
DATA OUT VALID
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23, 24]
A D D R ES S
tR C
CE
t PD
t H Z CE
tACE
OE
t HZOE
t DO E
t LZ O E
BH E/
B LE
t DB E
t LZ B E
D A TA I / O
H IG H IM PE D A N C E
t H Z BE
D ATA O U T V ALID
H IG H
IM P ED AN C E
t LZ C E
V CC
SU PP LY
CURRENT
tP U
IS B
Notes
21. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
22. WE is HIGH for Read cycle.
23. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
24. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95424 Rev. *E
Page 11 of 20
CY62147G/CY621472G
MoBL® Automotive
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled) [25, 26, 27]
tWC
ADDRESS
t SCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
t PWE
WE
t HZWE
DATA I/O
tSD
t LZWE
tHD
DATA IN VALID
Notes
25. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
26. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
27. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-95424 Rev. *E
Page 12 of 20
CY62147G/CY621472G
MoBL® Automotive
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (CE Controlled) [28, 29, 30]
tW C
ADDRESS
tS A
tSCE
CE
tA W
tH A
t PW E
WE
tB W
BHE /
BLE
OE
t HZO E
tH D
tS D
DATA I /O
D A T A IN V A L ID
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [28, 29, 30, 31]
t WC
ADDRESS
t SCE
CE
tBW
BHE /
BLE
tSA
tAW
tHA
t PWE
WE
t LZW E
t HZW E
DATA I /O
tSD
tHD
DATA IN VALID
Notes
28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
30. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
31. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95424 Rev. *E
Page 13 of 20
CY62147G/CY621472G
MoBL® Automotive
Switching Waveforms (continued)
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled) [32, 33, 34]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
tLZWE
DATAIN VALID
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
34. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-95424 Rev. *E
Page 14 of 20
CY62147G/CY621472G
MoBL® Automotive
Truth Table – CY62147G/CY621472G
CE / CE1
H
CE2
WE
OE
BHE
BLE
[35]
X
X
X
X
X
X[35]
Inputs/Outputs
Mode
Power
HI-Z
Deselect/Power-down
Standby (ISB)
L
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
[35]
X
X
H
H
HI-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
HI-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
HI-Z
Output disabled
Active (ICC)
L
H
H
H
H
L
HI-Z
Output disabled
Active (ICC)
L
H
H
H
L
L
HI-Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
HI-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
[35]
X
X
Note
35. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-95424 Rev. *E
Page 15 of 20
CY62147G/CY621472G
MoBL® Automotive
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
2.2 V–3.6 V CY62147G30-45BVXA
Package Type
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable,
Tape and Reel
CY62147G30-45ZSXA
51-85087 44-pin TSOP II without ERR
CY62147G30-45ZSXAT
51-85087 44-pin TSOP II without ERR, Tape and Reel
CY621472G30-45ZSXA
51-85087 44-pin TSOP II, Dual Chip Enable
2.2 V–3.6 V CY62147G30-55BVXE
Operating
Range
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable Automotive-A
CY62147G30-45BVXAT
CY621472G30-45ZSXAT
55
Package
Diagram
51-85087 44-pin TSOP II, Dual Chip Enable, Tape and Reel
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable Automotive-E
CY62147G30-55BVXET
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable,
Tape and Reel
CY62147G230-55ZSXE
51-85087 44-pin TSOP II, Dual Chip Enable
CY62147G230-55ZSXET
51-85087 44-pin TSOP II, Dual Chip Enable, Tape and Reel
CY62147G30-55ZSXE
51-85087 44-pin TSOP II
CY62147G30-55ZSXET
51-85087 44-pin TSOP II, Tape and Reel
Ordering Code Definitions
CY 621
4
7
X G
E
30 - XX XX X X X
X= blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: X = A or E
A = Automotive-A, E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage range: 30 = 3 V typ
ERR output: Single-bit error correction indicator
Process Technology: G = 65 nm
Chip Enable: X = blank or 2
blank = Single Chip Enable; 2 = Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-95424 Rev. *E
Page 16 of 20
CY62147G/CY621472G
MoBL® Automotive
Package Diagrams
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Figure 13. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-95424 Rev. *E
Page 17 of 20
CY62147G/CY621472G
MoBL® Automotive
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
VFBGA
Very Fine-Pitch Ball Grid Array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-95424 Rev. *E
Symbol
Unit of Measure
Page 18 of 20
CY62147G/CY621472G
MoBL® Automotive
Document History Page
Document Title: CY62147G/CY621472G MoBL® Automotive, 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting
Code (ECC)
Document Number: 001-95424
Rev.
ECN No.
Orig. of
Change
Submission
Date
*B
5032662
NILE
12/01/2015
Changed status from Preliminary to Final.
*C
5428830
NILE
09/07/2016
Updated Maximum Ratings:
Updated Note 5 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to Operating Range “2.7 V to 3.6 V” and Test Condition
“VCC = Min, IOH = –1.0 mA”.
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*D
5997948
AESATMP8
12/18/2017
Updated logo and Copyright.
*E
6119305
NILE
04/02/2018
Updated Features:
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Completing Sunset Review.
Document Number: 001-95424 Rev. *E
Description of Change
Page 19 of 20
CY62147G/CY621472G
MoBL® Automotive
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© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-95424 Rev. *E
Revised April 2, 2018
Page 20 of 20
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