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CY62147G/CY621472G
CY62147GE MoBL®
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed: 45 ns/55 ns
■
Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Embedded ECC for single-bit error correction[1, 2]
■
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V
to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY62147G and CY62147GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62147GE device includes an
ERR pin that signals an error-detection and correction event
during a read cycle.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are de-asserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
On the CY62147GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table – CY62147G/CY62147GE on page 16 for a complete
description of read and write modes.
The logic block diagrams are on page 2.
Product Portfolio
Product[3]
Features and
Options
(see the Pin
Configurations
section)
CY62147G(E)18 Single or dual
CY62147G(E)30 Chip Enables
CY621472G30
Optional ERR
CY62147G(E)
pin
Power Dissipation
Range
Industrial
VCC Range (V)
Speed (ns)
Operating ICC, (mA)
f = fmax
Standby, ISB2 (µA)
Typ[4]
Max
Typ[4]
Max
1.65 V–2.2 V
55
15
20
3.5
10
2.2 V–3.6 V
45
15
20
3.5
8.7
4.5 V–5.5 V
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate 2001 V
Latch-up current ..................................................... >140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
to ground potential [8] .......................... –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z state [8] ..................................... –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
Output HIGH
voltage
VIH
VIL
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
45 ns / 55 ns
Min
Typ
Max
1.4
–
–
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V
VCC = Min, IOH = –0.1 mA
2
–
–
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
VCC = Min, IOH = –0.1 mA
– 0.5[9]
–
–
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V
VCC = Min, IOL = 0.1 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
1.4
–
VCC + 0.2[8]
+ 0.3[8]
4.5 V to 5.5 V
VOL
Test Conditions
VCC
1.65 V to 2.2 V –
2.2 V to 2.7 V
–
1.8
–
VCC
2.7 V to 3.6 V
–
2
–
VCC + 0.3[8]
4.5 V to 5.5 V
–
2.2
–
VCC + 0.5[8]
–0.2[8]
–
0.4
[8]
1.65 V to 2.2 V –
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3[8]
–
0.8
–
[8]
–
0.8
4.5 V to 5.5 V
–0.5
Unit
V
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC,
Output disabled
–1
–
+1
A
ICC
VCC operating supply current
Max VCC, IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
–
15
20
mA
f = 18.18 MHz
(55 ns)
–
15
20
mA
f = 1 MHz
–
3.5
6
mA
Notes
8. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
9. This parameter is guaranteed by design and not tested.
Document Number: 001-92847 Rev. *K
Page 7 of 22
CY62147G/CY621472G
CY62147GE MoBL®
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
ISB1[10]
Description
45 ns / 55 ns
Test Conditions
Min
Typ
Max
Automatic power down
current – CMOS inputs;
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VCC = 2.2 V to 3.6 V and 4.5 V to
5.5 V
(BHE and BLE) > VCC – 0.2 V,
–
3.5
8.7
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
–
–
10
25 °C [11]
–
3.5
3.7
[11]
–
–
4.8
70 °C [11]
–
–
7
–
–
8.7
25 °C [11]
–
3.5
4.3
40 °C
[11]
–
–
5
70 °C
[11]
–
–
7.5
–
–
10
VIN > VCC – 0.2 V, VIN < 0.2 V,
Unit
A
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
ISB2
[10]
Automatic power down
current – CMOS inputs
CE1 > VCC – 0.2V or
VCC = 2.2 V to 3.6 V and 4.5 V to CE2 < 0.2 V,
5.5 V
(BHE and BLE) >
VCC – 0.2 V,
40 °C
A
85 °C
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2V or
CE2 < 0.2 V or
(BHE and BLE) >
VCC – 0.2 V,
85 °C
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
Notes
10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-92847 Rev. *K
Page 8 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Capacitance
Parameter [12]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.35
68.85
°C/W
14.74
15.97
°C/W
AC Test Loads and Waveforms
Figure 8. AC Test Loads and Waveforms[13]
R1
VCC
OUTPUT
VHIGH
GND
R2
30 pF*
*Including
jig and sope
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-92847 Rev. *K
Page 9 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
Description
VDR
VCC for data retention
ICCDR[15, 16]
Data retention current
Conditions
VCC = 1.2 V
Min
Typ[14]
Max
Unit
1
–
–
V
–
–
13
A
0
–
–
ns
45/55
–
–
ns
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[17]
Chip deselect to data retention
time
tR[18]
Operation recovery time
Data Retention Waveform
Figure 9. Data Retention Waveform [19]
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
C E 1 o r
B H E . B L E
CE2
Notes
14. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
15. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
16. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
17. These parameters are guaranteed by design.
18. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
19. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-92847 Rev. *K
Page 10 of 22
CY62147G/CY621472G
CY62147GE MoBL®
AC Switching Characteristics
Parameter [20, 21]
Description
45 ns
55 ns
Unit
Min
Max
Min
Max
45
–
55
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid / Address to ERR valid
–
45
–
55
ns
tOHA
Data hold from address change / ERR hold from
address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
–
45
–
55
ns
tDOE
OE LOW to data valid / OE LOW to ERR valid
–
22
–
25
ns
5
–
5
–
ns
–
18
–
18
ns
impedance[21, 23]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to HI-Z[21, 22, 23]
tLZCE
10
–
10
–
ns
CE1 HIGH and CE2 LOW to
HI-Z[21, 22, 23]
–
18
–
18
ns
tPU
CE1 LOW and CE2 HIGH to
power-up[23]
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down[23]
–
45
–
55
ns
tDBE
BLE / BHE LOW to data valid
–
45
–
55
ns
5
–
5
–
ns
–
18
–
18
ns
tHZCE
tLZBE
tHZBE
CE1 LOW and CE2 HIGH to Low
impedance[21, 23]
BLE / BHE LOW to Low
BLE / BHE HIGH to
impedance[21, 23]
HI-Z[21, 22, 23]
Write Cycle[24, 25]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
45
–
ns
tAW
Address setup to write end
35
–
45
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE / BHE LOW to write end
35
–
45
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to
HI-Z[21, 22, 23]
WE HIGH to Low
impedance[21, 23]
Notes
20. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
21. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
22. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
23. These parameters are guaranteed by design.
24. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
25. The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-92847 Rev. *K
Page 11 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Switching Waveforms
Figure 10. Read Cycle No. 1 of CY62147G (Address Transition Controlled) [26, 27]
tRC
ADDRESS
tAA
t OHA
DATA I / O
PREVIOUS DATA OUT
VALID
DATA OUT VALID
Figure 11. Read Cycle No. 1 of CY62147GE (Address Transition Controlled) [26, 27]
t RC
ADDRESS
tAA
t OHA
DATA I
/O
PREVIOUS DATA OUT VALID
DATA OUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
26. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
27. WE is HIGH for Read cycle.
Document Number: 001-92847 Rev. *K
Page 12 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Switching Waveforms (continued)
Figure 12. Read Cycle No. 2 (OE Controlled) [28, 29, 30]
A D D R ES S
tR C
CE
t PD
t H Z CE
tACE
OE
t HZOE
t DO E
t LZ O E
BH E/
B LE
t DB E
t LZ B E
D A TA I / O
t H Z BE
H IG H IM PE D A N C E
H IG H
IM P ED AN C E
D ATA O U T V ALID
t LZ C E
tP U
V CC
SU PP LY
CURRENT
IS B
Figure 13. Write Cycle No. 1 (WE Controlled) [29, 31, 32]
tWC
ADDRESS
t SCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
t PWE
WE
t HZWE
DATA I/O
tSD
t LZWE
tHD
DATA IN VALID
Notes
28. WE is HIGH for Read cycle.
29. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
30. Address valid prior to or coincident with CE LOW transition.
31. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
32. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-92847 Rev. *K
Page 13 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Switching Waveforms (continued)
Figure 14. Write Cycle No. 2 (CE Controlled) [33, 34, 35]
tW C
ADDRESS
tS A
tSCE
CE
tA W
tH A
t PW E
WE
tB W
BHE /
BLE
OE
t HZO E
tH D
tS D
DATA I /O
D A T A IN V A L ID
Figure 15. Write Cycle No. 3 (WE Controlled, OE LOW) [33, 34, 35, 36]
t WC
ADDRESS
t SCE
CE
tBW
BHE /
BLE
tSA
tAW
tHA
t PWE
WE
t LZW E
t HZW E
DATA I /O
tSD
tHD
DATA IN VALID
Notes
33. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
34. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
35. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
36. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-92847 Rev. *K
Page 14 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Switching Waveforms (continued)
Figure 16. Write Cycle No. 4 (BHE/BLE Controlled) [37, 38, 39]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
tLZWE
DATAIN VALID
Notes
37. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
39. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 001-92847 Rev. *K
Page 15 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Truth Table – CY62147G/CY62147GE
CE1/CE[40] CE2[40]
WE
OE
BHE
BLE
[41]
Mode
Power
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
X
L
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
X
X
X
X
H
H
HI-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
HI-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
HI-Z
Output disabled
Active (ICC)
L
H
H
H
H
L
HI-Z
Output disabled
Active (ICC)
L
H
H
H
L
L
HI-Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
HI-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
H
X
Inputs/Outputs
ERR Output – CY62147GE
Output [42]
Mode
0
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
HI-Z
Device deselected/outputs disabled/Write operation
Notes
40. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH
41. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
42. ERR is an Output pin.If not used, this pin should be left floating
Document Number: 001-92847 Rev. *K
Page 16 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
2.2 V–3.6 V CY62147G30-45BVXI
Package Type
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR
CY62147G30-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR, Tape and Reel
CY62147GE30-45BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR
CY62147GE30-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR, Tape and Reel
CY62147G30-45ZSXI
51-85087 44-pin TSOP II without ERR
CY62147G30-45ZSXIT
51-85087 44-pin TSOP II without ERR, Tape and Reel
CY62147GE30-45ZSXI
51-85087 44-pin TSOP II with ERR
CY62147GE30-45ZSXI
51-85087 44-pin TSOP II with ERR, Tape and Reel
CY62147G30-45B2XI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Dual Chip Enable
without ERR
CY62147G30-45B2XIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Dual Chip Enable
without ERR, Tape and Reel
CY621472G30-45ZSXI
51-85087 44-pin TSOP II without ERR, Dual Chip Enable
CY621472G30-45ZSXIT
51-85087 44-pin TSOP II without ERR, Dual Chip Enable, Tape
and Reel
4.5 V–5.5 V CY62147G-45ZSXI
55
Package
Diagram
51-85087 44-pin TSOP II without ERR, Tape and Reel
CY62147GE-45ZSXI
51-85087 44-pin TSOP II with ERR
CY62147GE-45ZSXIT
51-85087 44-pin TSOP II with ERR, Tape and Reel
CY62147G-45BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR
CY62147G-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR, Tape and Reel
CY62147GE-45BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR
CY62147GE-45BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR, Tape and Reel
51-85087 44-pin TSOP II without ERR
CY62147G18-55ZSXT
51-85087 44-pin TSOP II without ERR, Tape and Reel
CY62147G18-55BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR
CY62147G18-55BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
without ERR, Tape and Reel
CY62147GE18-55ZSXI
51-85087 44-pin TSOP II with ERR
CY62147GE18-55ZSXIT
51-85087 44-pin TSOP II with ERR, Tape and Reel
CY62147GE18-55BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR
CY62147GE18-55BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
with ERR, Tape and Reel
Document Number: 001-92847 Rev. *K
Industrial
51-85087 44-pin TSOP II without ERR
CY62147G-45ZSXIT
1.8 V–2.2 V CY62147G18-55ZSXI
Operating
Range
Page 17 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Ordering Code Definitions
CY 621
4
7
G
E
XX - XX XX X I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = BV or ZS or B2
BV = 48-ball VFBGA (Single Chip enable)
ZS = 44-pin TSOP II
B2 = 48-ball VFBGA (Dual Chip enable)
Speed Grade: XX = 45 ns or 55 ns
Voltage Range: XX = 30 or 18 or No digits
30 = 3 V typ; 18 = 1.8 V typ; No digits = 5 V typ
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Bus width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-92847 Rev. *K
Page 18 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Package Diagrams
Figure 17. 44-pin TSOP II (Z44) Package Outline, 51-85087
51-85087 *E
Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-92847 Rev. *K
Page 19 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
VFBGA
Very Fine-Pitch Ball Grid Array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-92847 Rev. *K
Symbol
Unit of Measure
Page 20 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Document History Page
Document Title: CY62147G/CY621472G/CY62147GE MoBL®, 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting
Code (ECC)
Document Number: 001-92847
Rev.
ECN No.
Orig. of
Change
Submission
Date
*F
4867081
NILE
07/31/2015
*G
4968879
NILE
10/16/2015
Fixed typo in bookmarks.
*H
5019226
VINI
11/18/2015
Updated Ordering Information:
Updated part numbers.
*I
5432584
NILE
09/10/2016
Updated Maximum Ratings:
Updated Note 8 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*J
5787633
NILE
06/27/2017
Updated to new template.
Completing Sunset Review.
*K
6245720
NILE
07/13/2018
Updated Features:
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-92847 Rev. *K
Description of Change
Changed status from Preliminary to Final.
Page 21 of 22
CY62147G/CY621472G
CY62147GE MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-92847 Rev. *K
Revised July 13, 2018
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 22 of 22
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