CY62147GN/CY621472GN MoBL®
4-Mbit (256K words × 16 bit) Static RAM
4-Mbit (256K words × 16 bit) Static RAM
Features
Functional Description
■
High speed: 45 ns/55 ns
■
Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
CY62147GN and CY621472GN are high-performance CMOS
low-power (MoBL) SRAM devices organized as 256K Words by
16-bits. Both devices are offered in single and dual chip enable
options and in multiple pin configurations.
■
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as low and CE2 as HIGH.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE1 HIGH/CE2 LOW for a dual chip enable device), or
control signals are de-asserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
The logic block diagram is provided in page 2.
Product Portfolio
Product
CY62147GN18
CY62147GN30
CY621472GN30
Features and
Options
(see the Pin
Configurations
section)
Single or dual
Chip Enables
Power Dissipation
Operating ICC, (mA)
Range
Industrial
CY62147GN
VCC Range (V)
Speed (ns)
f = fmax
Standby, ISB2 (µA)
Typ[1]
Max
Typ[1]
Max
1.65 V–2.2 V
55
15
20
3.5
10
2.2 V–3.6 V
45
15
20
3.5
8.7
4.5 V–5.5 V
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 002-10624 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 21, 2017
CY62147GN/CY621472GN MoBL®
Logic Block Diagram – CY62147GN
MEMORY
ARRAY
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
OE
CE2
CE1
BLE
Document Number: 002-10624 Rev. *D
Page 2 of 20
CY62147GN/CY621472GN MoBL®
Contents
Pin Configuration – CY62147GN ..................................... 4
Pin Configuration – CY621472GN ................................... 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
AC Switching Characteristics ....................................... 10
Switching Waveforms .................................................... 11
Truth Table – CY62147GN/CY621472GN ...................... 15
Document Number: 002-10624 Rev. *D
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
CY62147GN/CY621472GN MoBL®
Pin Configuration – CY62147GN
Figure 1. 48-ball VFBGA pinout (Dual Chip Enable),
CY62147GN[2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
I/O8
BHE
A3
A4
CE1
I/O9
I/O10
A5
A6
VSS
I/O11
A17
VCC
I/O12
I/O14
Figure 2. 48-ball VFBGA pinout (Single Chip Enable),
CY62147GN[2]
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
I/O0
B
I/O8
BHE
A3
A4
CE
I/O0
B
I/O1
I/O2
C
I/O9
I/O10
A5
A6
I/O1
I/O2
C
A7
I/O3
VCC
D
VSS
I/O11
A17
A7
I/O3
VCC
D
NC
A16
I/O4
Vss
E
VCC
I/O12
NC
A16
I/O4
Vss
E
I/O13
A14
A15
I/O5
I/O6
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
H
Figure 3. 44-pin TSOP II Pinout (Single Chip Enable), CY62147GN[2]
A4
A3
A2
A1
A0
/ CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44- TSOP-II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Notes
2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 002-10624 Rev. *D
Page 4 of 20
CY62147GN/CY621472GN MoBL®
Pin Configuration – CY621472GN
Figure 4. 44-pin TSOP II pinout (Dual Chip Enable), CY621472GN
A4
A3
A2
A1
A0
/CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
Document Number: 002-10624 Rev. *D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44- TSOP-II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
CE2
A8
A9
A10
A11
A12
Page 5 of 20
CY62147GN/CY621472GN MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential[3] ........................... –0.5 V to VCC + 0.5 V
Output current into outputs (in low state) .................... 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
DC voltage applied to outputs
in HI-Z state[3] ...................................... –0.5 V to VCC + 0.5 V
DC input voltage[3] .............................. –0.5 V to VCC + 0.5 V
Grade
Industrial
Ambient Temperature
VCC
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Test Conditions
Typ
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
1.4
–
–
2
–
–
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC – 0.5[4]
–
–
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V
VCC = Min, IOL = 0.1 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
1.65 V to 2.2 V –
1.4
–
VCC + 0.2[3]
2.2 V to 2.7 V
–
1.8
–
VCC + 0.3[3]
2.7 V to 3.6 V
–
2
–
VCC + 0.3[3]
4.5 V to 5.5 V
–
2.2
–
VCC + 0.5[3]
–0.2[3]
–
0.4
[3]
1.65 V to 2.2 V –
VIL
Input LOW
voltage
45/55 ns
Min
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3[3]
–
0.8
4.5 V to 5.5 V
–
–0.5[3]
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC,
Output disabled
–1
–
+1
A
f=
22.22 MHz
(45 ns)
–
15
20
mA
f=
18.18 MHz
(55 ns)
–
15
20
mA
f = 1 MHz
–
3.5
6
mA
ICC
VCC operating supply current
Max VCC, IOUT = 0 mA,
CMOS levels
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. This parameter is guaranteed by design and not tested.
Document Number: 002-10624 Rev. *D
Page 6 of 20
CY62147GN/CY621472GN MoBL®
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
Description
45/55 ns
Test Conditions
Automatic power down
current – CMOS inputs;
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
VCC = 2.2 V to 3.6 V and 4.5 V to
5.5 V
(BHE and BLE) > VCC – 0.2 V,
ISB1[5]
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
Min
Typ
Max
–
3.5
8.7
Unit
A
VIN > VCC – 0.2 V or VIN < 0.2 V,
–
–
10
25 °C[6]
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
–
3.5
3.7
CE1 > VCC – 0.2 V or
40
°C[6]
–
–
4.8
CE2 < 0.2 V or
70 °C[6]
–
–
7
85 °C
–
–
8.7
25 °C[6]
–
3.5
4.3
40 °C[6]
–
–
5
[6]
70 °C
–
–
7.5
85 °C
–
–
10
Automatic power down
(BHE and BLE) >
current – CMOS inputs
VCC = 2.2 V to 3.6 V and 4.5 V to VCC – 0.2 V,
5.5 V
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
ISB2[5]
CE1 > VCC – 0.2V or
CE2 < 0.2 V or
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
A
(BHE and BLE) >
VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, Max VCC
Notes
5. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
6. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 002-10624 Rev. *D
Page 7 of 20
CY62147GN/CY621472GN MoBL®
Capacitance
Parameter[7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Parameter[7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
31.35
68.85
°C/W
14.74
15.97
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms[8]
R1
VCC
OUTPUT
VHIGH
GND
R2
30 pF*
*Including
jig and sope
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
Parameters
1.8 V
2.5 V
R1
13500
R2
10800
RTH
6000
8000
VTH
0.80
1.20
RTH
VTH
3.0 V
5.0 V
Unit
16667
1103
1800
15385
1554
990
645
639
1.75
1.77
V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 002-10624 Rev. *D
Page 8 of 20
CY62147GN/CY621472GN MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
VDR
Description
Conditions
VCC for data retention
Min
Typ[9]
Max
Unit
1
–
–
V
13
A
Vcc = 1.2 V,
ICCDR[10, 11]
CE1 > VCC 0.2 V or CE2 < 0.2 V
Data retention current
or (BHE and BLE) > VCC – 0.2 V,
–
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR[12]
Chip deselect to data retention
time
tR[13]
Operation recovery time
0
–
–
ns
45/55
–
–
ns
Data Retention Waveform
Figure 6. Data Retention Waveform[14]
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
C E 1 o r
B H E . B L E
CE2
Notes
9. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
12. These parameters are guaranteed by design.
13. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 002-10624 Rev. *D
Page 9 of 20
CY62147GN/CY621472GN MoBL®
AC Switching Characteristics
Parameter[15, 16]
Description
45 ns
55 ns
Min
Max
Min
Max
Unit
READ CYCLE
tRC
Read cycle time
45
–
55
–
ns
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
tLZOE
OE LOW to Low
impedance[17]
HI-Z[17, 18]
tHZOE
OE HIGH to
tLZCE
CE1 LOW and CE2 HIGH to Low impedance[17]
HI-Z[17, 18]
–
18
–
18
ns
10
–
10
–
ns
–
18
–
18
ns
tHZCE
CE1 HIGH and CE2 LOW to
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
45
–
55
ns
tDBE
BLE / BHE LOW to data valid
–
45
–
55
ns
5
–
5
–
ns
–
18
–
18
ns
tLZBE
tHZBE
WRITE
BLE / BHE LOW to Low
BLE / BHE HIGH to
impedance[17]
HI-Z[17, 18]
CYCLE[19, 20]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
45
–
ns
tAW
Address setup to write end
35
–
45
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tBW
BLE / BHE LOW to write end
35
–
45
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to
HI-Z[17, 18]
WE HIGH to Low
impedance[17]
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
16. These parameters are guaranteed by design.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
20. The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 002-10624 Rev. *D
Page 10 of 20
CY62147GN/CY621472GN MoBL®
Switching Waveforms
Figure 7. Read Cycle No. 1 of CY62147GN (Address Transition Controlled)[21, 22]
tRC
ADDRESS
tAA
t OHA
PREVIOUS DATA OUT
VALID
DATA I / O
DATA OUT VALID
Figure 8. Read Cycle No. 2 (OE Controlled)[21, 22, 23, 24]
A D D R ES S
tR C
CE
t PD
t H Z CE
tACE
OE
t HZOE
t DO E
t LZ O E
BH E/
B LE
t DB E
t LZ B E
D A TA I / O
H IG H IM PE D A N C E
t H Z BE
D ATA O U T V ALID
H IG H
IM P ED AN C E
t LZ C E
V CC
SU PP LY
CURRENT
tP U
IS B
Notes
21. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
22. WE is HIGH for Read cycle.
23. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
24. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-10624 Rev. *D
Page 11 of 20
CY62147GN/CY621472GN MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 1 (WE Controlled)[25, 26, 27]
tWC
ADDRESS
t SCE
CE
tBW
BHE/
BLE
tAW
tSA
tHA
t PWE
WE
t HZWE
DATA I/O
tSD
t LZWE
tHD
DATA IN VALID
Notes
25. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
26. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
27. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 002-10624 Rev. *D
Page 12 of 20
CY62147GN/CY621472GN MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 2 (CE Controlled)[28, 29, 30]
tW C
ADDRESS
tS A
tSCE
CE
tA W
tH A
t PW E
WE
tB W
BHE /
BLE
OE
t HZO E
tH D
tS D
DATA I /O
D A T A IN V A L ID
Figure 11. Write Cycle No. 3 (WE Controlled, OE LOW)[28, 29, 30, 31]
t WC
ADDRESS
t SCE
CE
tBW
BHE /
BLE
tAW
tSA
tHA
t PWE
WE
t LZW E
t HZW E
DATA I /O
tSD
tHD
DATA IN VALID
Notes
28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
30. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
31. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 002-10624 Rev. *D
Page 13 of 20
CY62147GN/CY621472GN MoBL®
Switching Waveforms (continued)
Figure 12. Write Cycle No. 4 (BHE/BLE Controlled)[32, 33, 34]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
tLZWE
DATAIN VALID
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
34. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
Document Number: 002-10624 Rev. *D
Page 14 of 20
CY62147GN/CY621472GN MoBL®
Truth Table – CY62147GN/CY621472GN
CE1/CE[35] CE2[35]
WE
OE
BHE
BLE
[36]
Mode
Power
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
X
L
X
X
X
X
HI-Z
Deselect/Power-down
Standby (ISB)
X
X
X
X
H
H
HI-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Read
Active (ICC)
L
H
H
L
L
H
HI-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
H
H
L
H
HI-Z
Output disabled
Active (ICC)
L
H
H
H
H
L
HI-Z
Output disabled
Active (ICC)
L
H
H
H
L
L
HI-Z
Output disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
HI-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
HI-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
H
X
Inputs/Outputs
Notes
35. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH
36. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 002-10624 Rev. *D
Page 15 of 20
CY62147GN/CY621472GN MoBL®
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
2.2 V–3.6 V
Package
Diagram
Operating
Range
Package Type
CY62147GN30-45BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Dual Chip Enable
CY62147GN30-45BVXIT
VFBGA (6 × 8 × 1 mm), Dual Chip Enable, Tape
51-85150 48-ball
and Reel
CY62147GN30-45ZSXI
51-85087 44-pin TSOP II, Single Chip Enable
CY62147GN30-45ZSXIT
51-85087 44-pin TSOP II, Single Chip Enable, Tape and Reel
CY62147GN30-45B2XI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
CY62147GN30-45B2XIT
VFBGA (6 × 8 × 1 mm), Single Chip Enable, Tape
51-85150 48-ball
and Reel
CY621472GN30-45ZSXI
51-85087 44-pin TSOP II, Dual Chip Enable
Industrial
CY621472GN30-45ZSXIT 51-85087 44-pin TSOP II, Dual Chip Enable, Tape and Reel
55
1.65 V–2.2 V
CY62147GN18-55BVXI
51-85150 48-ball VFBGA (6 × 8 × 1 mm), Single Chip Enable
CY62147GN18-55BVXIT
VFBGA (6 × 8 × 1 mm), Single Chip Enable, Tape
51-85150 48-ball
and Reel
Ordering Code Definitions
CY 621
4
7
X GN XX - XX XX X X
X
X: T = Tape and Reel; Blank = Bulk
Temperature Grade: X = I; I = Industrial
Pb-free
Package Type: XX = BV, B2 or ZS
BV = 48-ball VFBGA (Dual Chip Enable);
B2 = 48-ball VFBGA (Single Chip Enable)
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
Voltage Range: 30 = 3 V typ
Process Technology: GN = 65 nm
Chip Enable: X = blank or 2
blank = Single Chip Enable; 2 = Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 002-10624 Rev. *D
Page 16 of 20
CY62147GN/CY621472GN MoBL®
Package Diagrams
Figure 13. 44-pin TSOP II (Z44) Package Outline, 51-85087
51-85087 *E
Figure 14. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 002-10624 Rev. *D
Page 17 of 20
CY62147GN/CY621472GN MoBL®
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degrees Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
A
microamperes
I/O
input/output
s
microseconds
OE
output enable
mA
milliamperes
SRAM
static random access memory
mm
millimeters
TSOP
thin small outline package
ns
nanoseconds
VFBGA
very fine-pitch ball grid array
ohms
WE
write enable
%
percent
pF
picofarads
V
volts
W
watts
Document Number: 002-10624 Rev. *D
Symbol
Unit of Measure
Page 18 of 20
CY62147GN/CY621472GN MoBL®
Document History Page
Document Title: CY62147GN/CY621472GN MoBL®, 4-Mbit (256K words × 16 bit) Static RAM
Document Number: 002-10624
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
5076421
NILE
01/07/2016
New data sheet.
*A
5084145
NILE
01/13/2016
Updated Logic Block Diagram – CY62147GN.
*B
5329364
VINI
06/29/2016
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*C
5429186
NILE
09/07/2016
Updated DC Electrical Characteristics: Enhanced VIH of 2.2V - 2.7V operating
range from 2.0V to 1.8V. Enhanced VOH of 2.7V - 3.6V operating range from
2.2V to 2.4V.
Updated Ordering Information: Updated part numbers.
Updated Note 3.
Updated Copyright and Disclaimer.
*D
6002285
AESATP12
12/21/2017
Updated logo and copyright.
Document Number: 002-10624 Rev. *D
Page 19 of 20
CY62147GN/CY621472GN MoBL®
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-10624 Rev. *D
Revised December 21, 2017
Page 20 of 20
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