CY62148BLL-70ZXI

CY62148DV30 4-Mb (512K x 8) MoBL Static RAM Functional Description[1] Features • Very high speed: 55 ns — Wide voltage range: 2.20V – 3.60V • Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 • Ultra low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • • — Typical active current: 8 mA @ f = fmax(55-ns speed) Ultra low standby power Easy memory expansion with CE, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered: 36-ball BGA, 32-pin TSOPII and 32-pin SOIC The CY62148DV30 is a high-performance CMOS static RAMs organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Logic Block Diagram I/O0 Data in Drivers I/O1 512K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A A6 A87 A A109 A11 A12 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A13 A14 A15 A16 A17 A18 WE OE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05341 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 10, 2004 CY62148DV30 Pin Configuration[2,3] FBGA 32 TSOPII Top View A0 I/O4 A1 Top View A6 A3 NC WE A4 DNU A5 A8 A I/O0 B I/O1 C VSS Vcc D VCC Vss E I/O2 F A2 I/O5 A18 I/O6 A7 A17 I/O7 OE CE A16 A15 I/O3 G A9 A10 A11 A12 A13 A14 H A 32 SOIC A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 4 32 31 30 29 5 6 28 27 7 8 9 10 11 12 26 25 1 2 3 13 14 15 16 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 A Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 4 32 31 30 29 5 6 28 27 7 8 9 10 11 12 26 25 1 2 3 13 14 15 16 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 Notes: 2. NC pins are not connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. Document #: 38-05341 Rev. *B Page 2 of 11 CY62148DV30 DC Input Voltage[4,5] ......................–0.3V to VCC(MAX) + 0.3V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................. –65°C to +150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................... 55°C to +125°C Operating Range Supply Voltage to Ground Potential ........................................ –0.3V to VCC(MAX) + 0.3V Product CY62148DV30L DC Voltage Applied to Outputs in High-Z State[4,5] ......................... –0.3V to VCC(MAX) + 0.3V Ambient Temperature Range VCC[6] Industrial –40°C to +85°C 2.2V to 3.6V CY62148DV30LL Product Portfolio Power Dissipation Operating ICC (mA) VCC Range (V) Max. Speed (ns) Typ.[7] 3.0 3.6 55 1.5 2.2 3.0 3.6 55 2.2 3.0 3.6 70 2.2 3.0 3.6 70 Min. Typ.[7] CY62148DV30L 2.2 CY62148DV30LL CY62148DV30L CY62148DV30LL Product f = 1 MHz f = fmax Max. Max. Typ.[7] Max. 3 8 15 2 12 2 12 3 1.5 Standby ISB2 (uA) Typ.[7] 10 3 8 8 15 3 10 8 Electrical Characteristics Over the Operating Range CY62148DV30-55 Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Min. Typ.[7] Test Conditions Max. CY62148DV30-70 Min. Typ.[7] Max. Unit IOH = –0.1 mA VCC = 2.20V 2.0 2.0 V IOH = –1.0 mA VCC = 2.70V 2.4 2.4 V IOL = 0.1 mA VCC = 2.20V 0.4 0.4 V IOL = 2.1 mA VCC = 2.70V 0.4 0.4 V VCC = 2.2V to 2.7V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current –1 +1 –1 +1 µA ICC VCC Operating Supply f = fMAX = 1/tRC VCC = VCCmax IOUT = 0 mA Current CMOS levels f = 1 MHz 15 mA GND < VO < VCC, Output Disabled L 8 LL L 15 8 10 10 mA mA 1.5 3 1.5 3 2 12 2 12 LL ISB1 ISB2 Automatic CE Power-down Current — CMOS Inputs L CE > VCC−0.2V, VIN>VCC–0.2V, VIN VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V L LL mA 8 2 12 µA 8 2 8 12 µA 8 Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05341 Rev. *B Page 3 of 11 CY62148DV30 Capacitance for all packages[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Max. Unit 10 pF 10 pF Thermal Resistance Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions BGA TSOP II SOIC STSOP Unit 72 75.13 55 105 °C/W 8.86 8.95 22 13 °C/W Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC 10% R2 50 pF 90% 10% 90% GND Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.50V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[8] tR[9] Min. Typ.[7] Max. Unit Conditions 1.5 VCC = 1.5V, CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V V L 9 µA LL 6 µA Chip Deselect to Data Retention Time Operation Recovery Time 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 1.5V VDR > 1.5 V tCDR 1.5V tR CE Notes: 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05341 Rev. *B Page 4 of 11 CY62148DV30 Switching Characteristics (Over the Operating Range)[10] 55 ns Parameter Description Min. 70 ns Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[11] tHZOE OE HIGH to High Z[11,12] tLZCE CE LOW to Low Z[11] 10 CE HIGH to High tPU CE LOW to Power-up tPD CE HIGH to Power-up ns 70 ns 70 ns 10 55 25 5 ns 35 5 20 10 Z[11, 12] tHZCE 70 55 25 10 20 0 ns ns 25 0 55 ns ns ns ns 70 ns Write Cycle[13] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 40 45 ns tAW Address Set-up to Write End 40 45 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z[11, 12] tLZWE WE HIGH to Low Z[11] 20 10 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. Document #: 38-05341 Rev. *B Page 5 of 11 CY62148DV30 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE DATA OUT tHZOE tHZCE tDOE tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% Write Cycle No. 1 (WE Controlled) ISB [17, 19] tWC ADDRESS tSCE CE tAW tSA WE tHA tPWE OE tSD DATA I/O NOTE 18 tHD DATAIN VALID tHZOE Notes: 16. Address valid prior to or coincident with CE transition LOW. 17. Data I/O is high impedance if OE = VIH. 18. During this period, the I/Os are in output state and input signals should not be applied. 19. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. Document #: 38-05341 Rev. *B Page 6 of 11 CY62148DV30 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[17, 19] tWC ADDRESS tSCE CE tHA tSA tAW tPWE WE OE tSD DATA I/O tHD DATAIN VALID Write Cycle No. 3 (WE Controlled, OE LOW) [19] tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tSD DATA I/O tHD DATAIN VALID NOTE 18 tLZWE tHZWE Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-down Standby (ISB) L H L Data Out (I/O0-I/O7) Read Active (ICC) L H H High Z Output Disabled Active (Icc) L L X Data in (I/O0-I/O7) Write Active (Icc) Ordering Information Speed (ns) 55 Ordering Code CY62148DV30L-55BVI Package Name Package Type Operating Range BV36A 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) Industrial BV36A 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) Pb-free Industrial ZS-32 32-pin TSOP II Pb-free Industrial S-32 32-pin SOIC Pb-free Industrial CY62148DV30LL-55BVI 55 CY62148DV30L-55BVXI CY62148DV30LL-55BVXI 55 CY62148DV30L-55ZSXI CY62148DV30LL-55ZSXI 55 CY62148DV30L-55SXI CY62148DV30LL-55SXI Document #: 38-05341 Rev. *B Page 7 of 11 CY62148DV30 Ordering Information (continued) Speed (ns) 70 Ordering Code CY62148DV30L-70BVI Package Name Operating Range Package Type BV36A 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) Industrial BV36A 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) Pb-free Industrial ZS-32 32-pin TSOP II Pb-free Industrial S-32 32-pin SOIC Pb-free Industrial CY62148DV30LL-70BVI 70 CY62148DV30L-70BVXI CY62148DV30LL-70BVXI 70 CY62148DV30L-70ZSXI CY62148DV30LL-70ZSXI 70 CY62148DV30L-70SXI CY62148DV30LL-70SXI Package Diagrams 36-Lead FBGA (6 x 8 x 1 mm) BV36A 51-85149-*B Document #: 38-05341 Rev. *B Page 8 of 11 CY62148DV30 Package Diagrams (continued) 32-Lead TSOP II ZS32 51-85095-** Document #: 38-05341 Rev. *B Page 9 of 11 CY62148DV30 Package Diagrams (continued) 32-Lead (450 MIL) Molded SOIC S34 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 0.023[0.584] 0.039[0.990] 0.047[1.193] 0.063[1.600] 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05341 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62148DV30 Document History Page Document Title:CY62148DV30 4-Mb (512K x 8) MoBL Static RAM Document Number: 38-05341 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 127480 06/17/03 HRT Created new data sheet *A 131041 01/23/04 CBD Change from Advance to Preliminary *B 222180 See ECN AJU Change from Preliminary to Final Added 70 ns speed bin Modified footnote #6 and #12 Removed MAX value for VDR on “Data Retention Characteristics” table Modified input and output capacitance values Added Pb-free ordering information Removed 32-pin STSOP package Document #: 38-05341 Rev. *B Page 11 of 11