CY62148BNLL

CY62148BN MoBL® 4-Mbit (512K x 8) Static RAM Features ■ ■ Functional Description The CY62148BN is a high performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power down feature that reduces power consumption by more than 99% when deselected. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) go into a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). 4.5V–5.5V operation Low active power ❐ Typical active current: 2.5 mA @ f = 1 MHz ❐ Typical active current:12.5 mA @ f = fmax Low standby current Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features CMOS for optimum speed and power Available in standard Pb-free and non Pb-free 32-lead (450-mil) SOIC and 32-lead TSOP II packages ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER I/O0 I/O1 A0 A1 A4 A5 A6 A7 A12 A14 A16 A17 ROW DECODER I/O2 SENSE AMPS 512 K x 8 ARRAY I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A2 A3 A15 A18 A13 A8 A9 A11 A10 Cypress Semiconductor Corporation Document Number : 001-06517 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 7, 2010 [+] Feedback CY62148BN MoBL® Contents Functional Description ..................................................... 1 Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics Over the Operating Range ..... 4 Capacitance[4] ................................................................... 4 AC Test Loads and Waveforms ....................................... 4 Switching Characteristics[5] Over the Operating Range . 5 Data Retention Characteristics (Over the Operating Range) 6 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 6 Read Cycle No. 1[10, 11] ............................................... 6 Read Cycle No. 2 (OE Controlled)[11, 12] ..................... 6 Write Cycle No. 1 (CE Controlled)[13] ............................. 7 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] ......................................................................... 7 Write Cycle No. 3 (WE Controlled, OE LOW)[13, 14] .... 8 Truth Table ........................................................................ 8 Ordering Information ........................................................ 8 Package Diagram .............................................................. 9 Document History PageSales, Solutions, and Legal Information .............................................................................. 10 Document Number : 001-06517 Rev. *D Page 2 of 10 [+] Feedback CY62148BN MoBL® Pin Configuration Top View SOIC TSOP II A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio VCC Range Product Min CY62148BNLL 4.5 V Typ 5.0V Max 5.5V 70 ns Speed Power Dissipation Operating ICC (mA) f = fmax Typ[1] 12.5 Max 20 Standby ISB2 (µA) Typ[1] 4 Max 20 Note 1. Typical values are measured at VCC = 5V, TA = 25 C, and are included for reference only and are not tested or guaranteed. Document Number : 001-06517 Rev. *D Page 3 of 10 [+] Feedback CY62148BN MoBL® Maximum Ratings Exceeding the maximum rating may impair the device’s useful life. User guidelines only and are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .......................................... –55 C to +125 C Supply Voltage on VCC to Relative GND ........–0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ..................................... –0.5V to VCC +0.5V DC Input Voltage[2] ................................. –0.5V to VCC +0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Industrial Ambient Temperature[3] –40 C to +85 C VCC 4.5V–5.5V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current – TTL Inputs Automatic CE Power Down Current – CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz IOUT = 0 mA VCC = Max., Test Conditions IOH = –1 mA IOL = 2.1 mA 2.2 –0.3 –1 –1 12.5 2.5 1.5 4 20 CY62148BN Min 2.4 0.4 VCC +0.3 0.8 +1 +1 20 Typ[1] Max Unit V V V V µA µA mA mA mA µA Max. VCC, CE > VIH VIN VIH or VIN < VIL, f = fMAX Max. VCC, CE  VCC – 0.3V, VIN  VCC – 0.3V, or VIN < 0.3V, f =0 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC – 5.0V Max. 6 8 Unit pF pF AC Test Loads and Waveforms R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 5 pF 990 INCLUDING JIG AND SCOPE (b) 3.0V R2 990 GND 3 ns Equivalent to: THEVENIN EQUIVALENT 639 1.77V OUTPUT R1 1800 ALL INPUT PULSES 90% 10% 90% 10%  3 ns (a) Notes 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 3. TA is the “instant on” case temperature 4. Tested initially and after any design or process changes that may affect these parameters. Document Number : 001-06517 Rev. *D Page 4 of 10 [+] Feedback CY62148BN MoBL® Switching Characteristics[5] Over the Operating Range Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[6] Z[6, 7] 70 60 60 0 0 55 30 0 5 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z [6] [6, 7] Description CY62148BN Min 70 70 10 70 35 5 25 10 25 0 70 Max Unit ns ns ns ns ns ns ns ns ns ns ns OE HIGH to High Z CE HIGH to High CE LOW to Low Z[6] Z[6, 7] CE LOW to Power Up CE HIGH to Power Down Notes 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. Document Number : 001-06517 Rev. *D Page 5 of 10 [+] Feedback CY62148BN MoBL® Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[4] tR [9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.3V VCC = VDR CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Min 2.0 Typ[1] Max 20 Unit V µA ns ns 0 tRC Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% ISB tHZOE tHZCE HIGH IMPEDANCE Notes 9. Full Device operation requires linear VCC ramp from VDR to VCC(min) > 100 ms or stable at VCC(min) > 100 ms. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number : 001-06517 Rev. *D Page 6 of 10 [+] Feedback CY62148BN MoBL® Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[13] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tHZCE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID tHD Notes 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 14. Data I/O is high-impedance if OE = VIH. 15. During this period the I/Os are in the output state and input signals should not be applied. Document Number : 001-06517 Rev. *D Page 7 of 10 [+] Feedback CY62148BN MoBL® Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[13, 14] tWC ADDRESS tSCE CE tHZCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H L L L OE X L X H WE X H L H I/O0–I/O7 High Z Data Out Data In High Z Power Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62148BNLL-70SXI Package Diagram 51-85081 Package Type 32-lead (450-Mil) Molded SOIC (Pb-Free) Operating Range Industrial Document Number : 001-06517 Rev. *D Page 8 of 10 [+] Feedback CY62148BN MoBL® Package Diagram Figure 1. 32-lead (450 Mil) Molded SOIC (51-85081) 51-85081 *C Document Number : 001-06517 Rev. *D Page 9 of 10 [+] Feedback CY62148BN MoBL® Document History Page Document Title: CY62148BN MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 001-06517 REV. ** *A *B ECN NO. 426504 485639 832320 Issue Date See ECN See ECN See ECN Orig. of Change NXR VKN NXR New Data Sheet Corrected the typo in the Array size in the Logic Block Diagram Removed Commercial Operating Range Removed 32-lead Reverse TSOP II package from product offering Corrected the test condition typo error in Electrical Characteristics table Updated Ordering information table Removed inactive parts from Ordering Information. Added Table of Contents. Updated Packaging Information Updated links in Sales, Solutions, and Legal Information. Removed unavailable parts. Description of Change *C 2896152 03/18/2010 AJU *D 2946367 06/07/2010 FSU © Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. Document Number : 001-06517 Rev. *D Revised June 7, 2010 Page 10 of 10 [+] Feedback