CY62148BN_09

CY62148BN MoBL® 4-Mbit (512K x 8) Static RAM Features • High Speed — 70 ns • 4.5V–5.5V operation • Low active power — Typical active current: 2.5 mA @ f = 1 MHz — Typical active current:12.5 mA @ f = fmax(70 ns) • Low standby current • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • CMOS for optimum speed/power • Available in standard lead-free and non-lead-free 32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead Reverse TSOP II packages Functional Description The CY62148BN is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). Logic Block Diagram I/O0 INPUT BUFFER A0 A1 A4 A5 A6 A7 A12 A14 A16 A17 I/O1 ROW DECODER I/O2 SENSE AMPS 512 K x 8 ARRAY I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A2 A3 A15 A18 A13 A8 A9 A11 A10 Cypress Semiconductor Corporation Document #: 001-06517 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 2, 2006 [+] Feedback CY62148BN MoBL® Pin Configuration Top View SOIC TSOP II A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Top View Reverse TSOP II GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A16 A17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE A11 A9 A8 A13 WE A18 A15 Vcc Product Portfolio Power Dissipation Operating, ICC VCC Range Product CY62148BNLL Min. 4.5 V Typ. 5.0V Max. 5.5V Speed 70 ns Temp. Com’l Ind’l Note: 1. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed. Standby (ISB2) Typ.[1] 4 µA Max. 20 µA f = fmax Typ.[1] 12.5 mA Max. 20 mA Document #: 001-06517 Rev. *A Page 2 of 10 [+] Feedback CY62148BN MoBL® Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] .....................................–0.5V to VCC +0.5V DC Input Voltage[2] ..................................–0.5V to VCC +0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature[3] 0°C to +70°C –40°C to +85°C VCC 4.5V–5.5V Electrical Characteristics Over the Operating Range CY62148BN-70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz Max. VCC,CE ≤ VIH VIN ≤ VIH or VIN ≤ VIL, f = fMAX Max. VCC, CE ≤ VCC – 0.3V, VIN ≤ VCC – 0.3V, or VIN ≤ 0.3V, f =0 Com’l/Ind’l IOUT =0 mA VCC = Max., Com’l/ Ind’l Com’l/ Ind’l 4 Test Conditions VCC = Min., IOH = – 1 mA VCC = Min., IOL = 2.1 mA 2.2 –0.3 –1 –1 12.5 2.5 1.5 Min. 2.4 0.4 VCC +0.3 0.8 +1 +1 20 Typ.[1] Max. Unit V V V V µA µA mA mA mA ISB1 ISB2 20 µA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF AC Test Loads and Waveforms R1 1800Ω 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 5 pF 990 Ω INCLUDING JIG AND SCOPE (b) 3.0V 90% R2 990 Ω GND ≤ 3 ns Equivalent to: THEVENIN EQUIVALENT 639 Ω 1.77V OUTPUT 10% 90% 10% ≤ 3 ns R1 1800Ω ALL INPUT PULSES (a) Notes: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 3. TA is the “Instant On” case temperature 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06517 Rev. *A Page 3 of 10 [+] Feedback CY62148BN MoBL® Switching Characteristics[5] Over the Operating Range 62148BNLL-70 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE CYCLE[8] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[6, 7] 70 60 60 0 0 55 30 0 5 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z [6] [6, 7] Description Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 ns ns ns ns ns ns ns ns ns ns OE HIGH to High Z [6] CE HIGH to High Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 001-06517 Rev. *A Page 4 of 10 [+] Feedback CY62148BN MoBL® Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[4] tR[9] Description VCC for Data Retention Data Retention Current Com’l LL Ind’l Operation Recovery Time LL No input may exceed VCC + 0.3V VCC = VDR = 3.0V CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Conditions Min. 2.0 20 20 0 tRC Typ.[1] Max. Unit V µA µA ns ns Chip Deselect to Data Retention Time Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No.1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB HIGH IMPEDANCE Notes: 9. Full Device operation requires linear VCC ramp from VDR to VCC(min) > 100 ms or stable at Vcc(min) > 100 ms. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 001-06517 Rev. *A Page 5 of 10 [+] Feedback CY62148BN MoBL® Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[13] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tHZCE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE Notes: 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. Data I/O is high-impedance if OE = VIH. 15. During this period the I/Os are in the output state and input signals should not be applied. tHD DATAIN VALID Document #: 001-06517 Rev. *A Page 6 of 10 [+] Feedback CY62148BN MoBL® Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW)[13, 14] tWC ADDRESS tSCE CE tHZCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H I/O0–I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 70 Ordering Code CY62148BNLL-70SC CY62148BNLL-70SXC CY62148BNLL-70ZC CY62148BNLL-70ZXC CY62148BNLL-70ZRC CY62148BNLL-70SI CY62148BNLL-70SXI CY62148BNLL-70ZI CY62148BNLL-70ZXI CY62148BNLL-70ZRI Package Diagram 51-85081 51-85081 51-85095 51-85095 51-85138 51-85081 51-85081 51-85095 51-85095 51-85138 Package Type 32-lead (450-Mil) Molded SOIC 32-lead (450-Mil) Molded SOIC (Pb-Free) 32-lead TSOP II 32-lead TSOP II (Pb-Free) 32-lead RTSOP II 32-lead (450-Mil) Molded SOIC 32-lead (450-Mil) Molded SOIC (Pb-Free) 32-lead TSOP II 32-lead TSOP II (Pb-Free) 32-lead RTSOP II Industrial Operating Range Commercial Please contact your local Cypress sales representative for availability of these parts Document #: 001-06517 Rev. *A Page 7 of 10 [+] Feedback CY62148BN MoBL® Package Diagrams 32 LD (450 Mil) SOIC32-lead (450-Mil) Molded SOIC (51-85081) 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms PART # S32.45 STANDARD PKG. SZ32.45 LEAD FREE PKG. MIN. MAX. 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B 32-Lead Thin Small Outline Package Type II (51-85095) 51-85095 ** Document #: 001-06517 Rev. *A Page 8 of 10 [+] Feedback CY62148BN MoBL® Package Diagrams (continued) 32-lead Reverse Thin Small Outline Package Type II (51-85138) 51-85138-** More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06517 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62148BN MoBL® Document History Page Document Title: CY62148BN MoBL® 4-Mbit (512K x 8) Static RAM Document Number: 001-06517 REV. ** *A ECN NO. 426504 485639 Issue Date See ECN See ECN Orig. of Change NXR VKN New Data Sheet Corrected the typo in the Array size in the Logic Block Diagram Description of Change Document #: 001-06517 Rev. *A Page 10 of 10 [+] Feedback