CY62148DV30
4-Mbit (512K x 8) MoBL Static RAM
Features
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Functional Description[1]
The CY62148DV30 is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH).The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when:
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Temperature Ranges ❐ Industrial: –40 °C to 85 °C Very high speed: 55 ns
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Wide voltage range: 2.20 V – 3.60 V
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Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 Ultra low active power
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Typical active current: 1.5 mA at f = 1 MHz Typical active current: 8 mA at f = fmax(55-ns speed)
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Ultra low standby power Easy memory expansion with CE, and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Available in Pb-free 32-pin Small-outline integrated circuit (SOIC package)
Deselected (CE HIGH) Outputs are disabled (OE HIGH) When the write operation is active(CE LOW and WE LOW)
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Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
CE WE OE
Data in Drivers
I/O0 I/O1
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A13 A14 A15 A16 A17 A18
Cypress Semiconductor Corporation Document Number : 38-05341 Rev. *F
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CY62148DV30
Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 6 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definition ............................................. 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document Number : 38-05341 Rev. *F
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CY62148DV30
Pin Configuration
32-pin SOIC Pinout
Top View
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62148DV30LL Industrial 2.2 Typ[2] 3.0 Max 3.6 55 Speed (ns) Operating ICC (mA) f = 1 MHz Typ[2] 1.5 Max 3 f = fmax Typ[2] 8 Max 10 Standby ISB2 (A) Typ[2] 2 Max 8
Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Maximum Ratings
(Exceeding maximum ratings may impair the useful life of the device. For user guidelines, not tested.) Storage temperature................................. –65 °C to +150 °C Ambient temperature with power applied ............................................. 55 °C to +125 °C supply voltage to ground potential ........................................–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High Z state[3, 4] ........................–0.3 V to VCC(max) + 0.3 V DC input voltage[3, 4]..................... –0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001V (per MIL-STD-883, method 3015) Latch-up current ..................................................... > 200 mA
Operating Range
Product CY62148DV30LL Range Industrial Ambient Temperature –40 °C to +85 °C VCC[5] 2.2 V to 3.6 V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH Description Output HIGH voltage IOH = –0.1 mA IOH = –1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.20 V VCC = 2.70 V VCC = 2.20 V VCC = 2.70 V 55 ns Min 2.0 2.4 – – 1.8 2.2 –0.3 –0.3 –1 –1 Typ[2] – – – – – – – – – – 8 – – 1.5 2 Max – – 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 10 3 8 Unit V V V V V V V V A A mA mA A
Output LOW voltage IOL = 0.1 mA
Input HIGH voltage VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V
VIL IIX IOZ ICC
Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic CE Power-down current — CMOS inputs Automatic CE Power-down current — CMOS inputs
VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.6 V GND < VI < VCC GND < VO < VCC, output disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels
ISB1
CE > VCC0.2 V, VIN>VCC–0.2 V, VIN VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V
ISB2
–
2
8
A
Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Capacitance
Parameter[6] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter[6] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOIC 55 22 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.5 V (2.2 V – 2.7 V) 16667 15385 8000 1.20
3.0 V (2.7 V – 3.6 V) 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[6] tR[8] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time VCC = 1.5 V, CE > VCC 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Conditions Min Typ[7] Max 1.5 – 0 55 – – – – 6 – – Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE
Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) 100 s.
1.5 V tCDR
VDR > 1.5 V
1.5 V tR
Document Number : 38-05341 Rev. *F
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Switching Characteristics (Over the Operating Range)
Parameter[9] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[12] Write cycle time CE LOW to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width Data set-up to write end Data hold from write end WE LOW to High Z[10, 11] WE HIGH to Low Z[10] 55 40 40 0 0 40 25 0 – 10 – – – – – – – – 20 – ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to Low Z[10] OE HIGH to High CE LOW to Low CE HIGH to High Z[10,11] Z[10, 11] Z[10] 55 – 10 – – 5 – 10 – 0 – – 55 – 55 25 – 20 – 20 – 55 ns ns ns ns ns ns ns ns ns ns ns Description 55 ns Min Max Unit
CE LOW to power-up CE HIGH to power-up
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes 9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Switching Waveforms
(continued) Figure 2. Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS CE tACE tRC
OE
tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID
tHZOE tHZCE
HIGH IMPEDANCE
tPD 50% ICC ISB
Figure 3. Write Cycle No. 1 (WE Controlled)[17, 18]
tWC ADDRESS CE tAW WE tSA tPWE tSCE
tHA
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Switching Waveforms
(continued) Figure 4. Write Cycle No. 2 (CE Controlled)[20, 21]
tWC
ADDRESS tSCE CE tSA tAW tPWE WE tHA
OE tSD DATA I/O DATAIN VALID tHD
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[21]
tWC
ADDRESS
tSCE
CE
tAW tHA tPWE tSD tHD tSA
WE
DATA I/O
NOTE 22
tHZWE
DATAIN VALID tLZWE
Truth Table
CE H L L L WE X H H L OE X L H X High Z Data out (I/O0-I/O7) High Z Data in (I/O0-I/O7) Inputs/Outputs Read Output disabled Write Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (Icc) Active (Icc)
Notes 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. 22. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Ordering Information
Speed (ns) 55 Ordering Code CY62148DV30LL-55SXI Package Diagram 51-85081 32-pin SOIC (Pb-free) Package Type Operating Range Industrial
Contact your local Cypress sales representative for availability of these parts
Ordering Code Definition
CY 621 4 8 D V30 LL 55 SX I Temperature Grade: I = Industrial Package Type: SX = 32 pin SOIC (Pb-free) Speed Grade LL = Low Power Voltage Range = 3 V typical D = Process Technology 130 nm Buswidth = × 8 Density = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress
Document Number : 38-05341 Rev. *F
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CY62148DV30
Package Diagrams
32-pin (450 MIL) Molded SOIC, 51-85081
51-85081 *C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document Number : 38-05341 Rev. *F
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CY62148DV30
Acronyms
Acronym CMOS I/O MoBL SOIC SRAM input/output more battery life small-outline integrated circuit static random access memory Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol ns V µA mA pF °C W volts micro amperes milli amperes pico Farad degree Celsius watts Unit of Measure nano seconds
Document Number : 38-05341 Rev. *F
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CY62148DV30
Document History Page
Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL Static RAM Document Number: 38-05341 REV. ** *A *B ECN NO. 127480 131041 222180 Issue Date 06/17/03 01/23/04 See ECN Orig. of Change HRT CBD AJU Created new data sheet Changed from Advance to Preliminary Changed from Preliminary to Final Added 70 ns speed bin Modified footnote #6 and #12 Removed MAX value for VDR on “Data Retention Characteristics” table Modified input and output capacitance values Added Pb-free ordering information Removed 32-pin STSOP package Added Automotive-A Operating Range Removed SOIC package from Product Offering Updated Ordering Information Table Added SOIC package and its related information Updated Ordering Information Table Removed inactive parts from Ordering Information. Added Table of Contents. Updated Packaging Information Updated links in Sales, Solutions, and Legal Information. Removed Automotive related info Removed 70 ns speed bin related info Remove TSOP and VFBGA package related info Updated as per new template Added Acronyms and Units of Measure table Added Ordering Code Definitiondetails Description of Change
*C
498575
See ECN
NXR
*D *E
729917 2896036
See ECN 03/19/10
VKN AJU
*F
3166059
02/08/2011
RAME
Document Number : 38-05341 Rev. *F
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CY62148DV30
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-05341 Rev. *F
Revised February 8, 2011
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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