CY62148G MoBL®
4-Mbit (512K words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed: 45 ns/55 ns
■
Ultra-low standby power
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
Device is accessed by asserting the chip enable (CE) input LOW.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O7 and
address on A0 through A18 pins.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O7).
■
Embedded ECC for single-bit error correction[1]
■
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Pb-free 32-pin SOIC and 32-pin TSOP II packages
All I/Os (I/O0 through I/O7) are placed in a HI-Z state when the
device is deselected (CE HIGH or control signal OE is
de-asserted).
See the Truth Table – CY62148G on page 12 for a complete
description of read and write modes.
The logic block diagrams are on page 2.
Functional Description
CY62148G is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC[1]. This device is offered
multiple pin configurations.
Logic Block Diagram – CY62148G
ECC DECODER
512K x 8
RAM ARRAY
DATAIN
DRIVERS
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
I/O0-I/O7
COLUMN DECODER
WE
A10
A11
A12
A13
A14
A15
A16
A17
A18
OE
CE
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation
Document Number: 001-95415 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2017
CY62148G MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics ......................................... 8
Switching Waveforms ...................................................... 9
Truth Table – CY62148G ................................................ 12
Document Number: 001-95415 Rev. *E
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62148G MoBL®
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 pin
TSOP II/
SOIC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A18
/WE
A13
A8
A9
A11
/OE
A10
/CE
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Product
CY62148G18
Range
Industrial
VCC Range (V)
Speed (ns)
Operating ICC, (mA)
f = fmax
Standby, ISB2 (µA)
Typ[2]
Max
Typ[2]
Max
1.65 V–2.2 V
55
–
20
–
10
CY62148G30
2.2 V–3.6 V
45
–
20
3.5
8.7
CY62148G
4.5 V–5.5 V
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 001-95415 Rev. *E
Page 3 of 17
CY62148G MoBL®
DC input voltage[3] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Output current into outputs (in low state) .................... 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
to ground potential[3] ............................–0.5 V to Vcc + 0.5 V
DC voltage applied to outputs
in HI-Z state[3] ...................................... –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC[4]
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
Output HIGH
voltage
VIH
VIL
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
Min
Typ
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
1.4
–
–
2.2 V to 2.7 V
VCC = Min, IOH = –0.1 mA
2
–
–
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.2
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
VCC = Min, IOH = –0.1 mA
– 0.5[5]
–
–
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
–
–
0.2
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 2.1 mA
4.5 V to 5.5 V
VOL
45 ns / 55 ns
Test Conditions
VCC
1.65 V to 2.2 V –
–
–
0.4
1.4
–
VCC + 0.2[3]
+ 0.3[3]
2.2 V to 2.7 V
–
1.8
–
VCC
2.7 V to 3.6 V
–
2
–
VCC + 0.3[3]
4.5 V to 5.5 V
–
2.2
–
VCC + 0.5[3]
–0.2[3]
–
0.4
[3]
–
0.6
[3]
–
0.8
1.65 V to 2.2 V –
2.2 V to 2.7 V
2.7 V to 3.6 V
–
–0.3
–
–0.3
[3]
Unit
V
V
V
V
–0.5
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
Max VCC, IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
–
–
20
mA
f = 18.18 MHz
(55 ns)
–
–
20
mA
f = 1 MHz
–
–
6
mA
4.5 V to 5.5 V
–
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
5. This parameter is guaranteed by design and not tested.
Document Number: 001-95415 Rev. *E
Page 4 of 17
CY62148G MoBL®
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
Parameter
ISB1[6]
Description
Automatic power down
current – CMOS inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
ISB2
[6]
Automatic power down
current – CMOS inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
45 ns / 55 ns
Test Conditions
Min
Typ
Max
–
–
8.7
–
–
10
25 °C [7]
–
3.5
3.7
40 °C
[7]
–
–
4.8
70 °C
[7]
–
–
7
–
–
8.7
25 °C [7]
–
3.5
4.3
40 °C
[7]
–
–
5
70 °C
[7]
–
–
7.5
–
–
10
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
Unit
A
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), Max VCC
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
A
85 °C
f = 0, Max VCC
Automatic power down
current – CMOS inputs
VCC = 1.65 V to 2.2 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
85 °C
f = 0, Max VCC
Notes
6. Chip enables (CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
7. The ISB2 limits at 25 °C, 40 °C, 70 °C, and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-95415 Rev. *E
Page 5 of 17
CY62148G MoBL®
Capacitance
Parameter [8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [8]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
32-pin SOIC
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
32-pin TSOP II Unit
51.79
79.03
°C/W
25.12
17.44
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [9]
R1
VCC
OUTPUT
VHIGH
GND
R2
30 pF*
*Including
jig and sope
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
1.8 V
2.5 V
3.0 V
5.0 V
Unit
R1
13500
16667
1103
1800
R2
10800
15385
1554
990
RTH
6000
8000
645
639
VTH
0.80
1.20
1.75
1.77
V
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95415 Rev. *E
Page 6 of 17
CY62148G MoBL®
Data Retention Characteristics
Over the Operating range
Parameter
Description
VDR
VCC for data retention
ICCDR[11, 12]
Data retention current
Conditions
VCC = 1.2 V,
Min
Typ [10]
Max
Unit
1
–
–
V
–
–
13
A
0
–
–
ns
45/55
–
–
ns
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR
[13, 14]
tR[14]
Chip deselect to data retention
time
Operation recovery time
Data Retention Waveform
Figure 3. Data Retention Waveform
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
CE
Notes
10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
11. Chip enables CE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. These parameters are guaranteed by design.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95415 Rev. *E
Page 7 of 17
CY62148G MoBL®
AC Switching Characteristics
Parameter [15, 16]
Description
45 ns
55 ns
Unit
Min
Max
Min
Max
45
–
55
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
–
55
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE LOW to data valid
–
45
–
55
ns
tDOE
OE LOW to data valid
–
22
–
25
ns
5
–
5
–
ns
–
18
–
18
ns
10
–
10
–
ns
–
18
–
18
ns
impedance[17]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to HI-Z[17, 18]
tLZCE
CE LOW to Low
impedance[17]
HI-Z[17, 18]
tHZCE
CE HIGH to
tPU
CE LOW to power-up
0
–
0
–
ns
tPD
CE HIGH to power-down
–
45
–
55
ns
Write Cycle
[19, 20]
tWC
Write cycle time
45
–
55
–
ns
tSCE
CE LOW to write end
35
–
45
–
ns
tAW
Address setup to write end
35
–
45
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
35
–
40
–
ns
tSD
Data setup to write end
25
–
25
–
ns
tHD
Data hold from write end
0
–
0
–
ns
–
18
–
20
ns
10
–
10
–
ns
tHZWE
tLZWE
WE LOW to
HI-Z[17, 18]
WE HIGH to Low
impedance[17]
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
16. These parameters are guaranteed by design.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL,All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
20. The minimum pulse width in Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-95415 Rev. *E
Page 8 of 17
CY62148G MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
t OHA
PREVIOUS DATA OUT
VALID
DATA I / O
DATA OUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [22, 23]
A D D R ES S
tR C
CE
t PD
t H Z CE
tACE
OE
t HZOE
t DO E
t LZ O E
BH E/
B LE
t DB E
t LZ B E
D A TA I / O
H IG H IM PE D A N C E
t H Z BE
D ATA O U T V ALID
H IG H
IM P ED AN C E
t LZ C E
V CC
SU PP LY
CURRENT
tP U
IS B
Notes
21. The device is continuously selected. OE = VIL, CE = VIL.
22. WE is HIGH for Read cycle.
23. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95415 Rev. *E
Page 9 of 17
CY62148G MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26]
tWC
ADDRESS
t SCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
t PWE
WE
t HZWE
DATA I/O
tSD
t LZWE
tHD
DATA IN VALID
Notes
24. WE is HIGH for Read cycle.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
26. Data I/O is in a HI-Z state if CE = VIH, or OE = VIH.
Document Number: 001-95415 Rev. *E
Page 10 of 17
CY62148G MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE Controlled) [27, 28]
tW C
ADDRESS
tS A
tSCE
CE
tA W
tH A
t PW E
WE
tB W
BHE /
BLE
OE
t HZO E
tH D
tS D
DATA I /O
D A T A IN V A L ID
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28, 29]
t WC
ADDRESS
t SCE
CE
tBW
BHE /
BLE
tSA
tAW
tHA
t PWE
WE
t LZW E
t HZW E
DATA I /O
tSD
tHD
DATA IN VALID
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
28. Data I/O is in HI-Z state if CE = VIH, or OE = VIH
29. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95415 Rev. *E
Page 11 of 17
CY62148G MoBL®
Truth Table – CY62148G
CE
H
WE
[30]
X
OE
Inputs/Outputs
[30]
HI-Z
X
L
H
L
Data Out (I/O0–I/O7)
L
H
H
HI-Z
L
[30]
Data In (I/O0–I/O7)
L
X
Mode
Power
Deselect/Power-down Standby (ISB)
Configuration
512 K × 8
Read
Active (ICC)
512 K × 8
Output disabled
Active (ICC)
512 K × 8
Write
Active (ICC)
512 K × 8
Note
30. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-95415 Rev. *E
Page 12 of 17
CY62148G MoBL®
Ordering Information
Speed
(ns)
45
Voltage
Range
Ordering Code
2.2 V–3.6 V
4.5 V–5.5 V
55
Package
Diagram
Package Type
CY62148G30-45SXI
51-85081 32-pin SOIC (450 Mils)
CY62148G30-45SXIT
51-85081 32-pin SOIC (450 Mils), Tape and Reel
CY62148G30-45ZSXI
51-85095 32-pin TSOP II
CY62148G30-45ZSXIT
51-85095 32-pin TSOP II, Tape and Reel
CY62148G-45SXI
51-85081 32-pin SOIC (450 Mils)
CY62148G-45SXIT
51-85081 32-pin SOIC (450 Mils), Tape and Reel
CY62148G-45ZSXI
51-85095 32-pin TSOP II
CY62148G-45ZSXIT
51-85095 32-pin TSOP II, Tape and Reel
1.65 V–2.2 V CY62148G18-55ZSXI
CY62148G18-55ZSXIT
Operating
Range
Industrial
51-85095 32-pin TSOP II
51-85095 32-pin TSOP II, Tape and Reel
Ordering Code Definitions
CY 621
4
8
G XX - XX XX X I
X
X: blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = S or ZS
S = 32-pin SOIC
ZS = 32-pin TSOP II
Speed Grade: XX: 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage Range: XX = 30 or 18 or no character
30 = 3 V typ; 18 = 1.8 V typ; no character = 5 V typ
Process Technology: G = 65 nm
Bus Width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-95415 Rev. *E
Page 13 of 17
CY62148G MoBL®
Package Diagrams
Figure 9. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
51-85081 *E
Figure 10. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
51-85095 *D
Document Number: 001-95415 Rev. *E
Page 14 of 17
CY62148G MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
megahertz
OE
output enable
A
microamperes
SRAM
static random access memory
s
microseconds
TSOP
thin small outline package
mA
milliamperes
VFBGA
very fine-pitch ball grid array
mm
millimeters
WE
write enable
ns
nanoseconds
ohms
%
percent
pF
picofarads
V
volts
W
watts
Document Number: 001-95415 Rev. *E
Symbol
Unit of Measure
Page 15 of 17
CY62148G MoBL®
Document History Page
Document Title: CY62148G MoBL®, 4-Mbit (512K words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-95415
Rev.
ECN No.
Orig. of
Change
Submission
Date
*B
5054381
NILE
12/17/2015
Changed status from Preliminary to Final.
*C
5082528
NILE
01/12/2016
Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*D
5432526
NILE
09/10/2016
Updated Maximum Ratings:
Updated Note 3 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E
5979578
AESATMP8
12/01/2017
Updated logo and Copyright.
Document Number: 001-95415 Rev. *E
Description of Change
Page 16 of 17
CY62148G MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95415 Rev. *E
Revised December 1, 2017
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