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The document following this cover page is marked as “Cypress” document as this is the
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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY62148GN MoBL®
4-Mbit (512K × 8) Static RAM
4-Mbit (512K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V, 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 3.5 µA
❐ Maximum standby current: 8.7 µA
■
Easy memory expansion with CE and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC) packages
The CY62148GN is a high-performance CMOS static RAM
organized as 512K words by 8-bits. This device features
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device in standby mode
reduces power consumption by more than 99% when deselected
(CE HIGH). The eight input and output pins (I/O0 through I/O7)
are placed in a high-impedance state when the device is
deselected (CE HIGH), Outputs are disabled (OE HIGH), or
during an active Write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For a complete list of related documentation, click here.
Logic Block Diagram
I/O00
IO
INPUT BUFFER
I/O1
IO
1
512K x 8
ARRAY
I/O3
IO
3
I/O4
IO
4
I/O5
IO
5
I/O6
IO
6
CE
•
I/O
IO77
POWER
DOWN
A17
A18
A15
A13
A14
OE
A16
COLUMN DECODER
WE
Cypress Semiconductor Corporation
Document Number: 001-95418 Rev. *D
I/O2
IO
2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 21, 2017
CY62148GN MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 001-95418 Rev. *D
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY62148GN MoBL®
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout
Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Product
CY62148GN30
Range
Industrial
CY62148GN
VCC Range (V)
2.2 V–3.6 V
Speed
(ns)
45
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (µA)
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
–
6
–
20
3.5
8.7
4.5 V–5.5 V
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-95418 Rev. *D
Page 3 of 15
CY62148GN MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Supply voltage to ground potential ......–0.5 V to Vcc + 0.5 V
Device
Range
DC voltage applied to outputs
in high Z state[2, 3] ................................–0.5 V to Vcc + 0.5 V
CY62148GN
Industrial
DC input voltage[2, 3] ............................–0.5 V to Vcc + 0.5 V
Ambient
Temperature
VCC[4]
–40 °C to +85 °C 2.2 V to 3.6 V,
4.5 V to 5.5 V
Electrical Characteristics
Over the operating range
Parameter
VOH
VOL
Description
Output HIGH
voltage
Test Conditions
Typ[5]
Max
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2
–
–
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA
VCC – 0.5[6]
–
–
Output LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
–
–
0.4
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
0.4
Input HIGH
voltage
2.2 V to 2.7 V –
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA
VIH
Input LOW
voltage
VIL
45 ns
Min
–
–
0.4
1.8
–
VCC + 0.3[3]
+ 0.3[3]
2.7 V to 3.6 V –
2
–
VCC
4.5 V to 5.5 V –
2.2
–
VCC + 0.5
2.2 V to 2.7 V –
–0.3[2]
–
0.6
2.7 V to 3.6 V –
–0.3[2]
–
0.8
4.5 V to 5.5 V –
–0.5
–
0.8
–1
–
+1
Unit
V
V
V
V
IIX
Input leakage current
GND < VI < VCC
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
µA
ICC
VCC operating supply current
f = fmax = 1/tRC
–
–
20
mA
–
–
6
–
3.5
8.7
µA
–
3.5
8.7
µA
f = 1 MHz
ISB1[7]
Automatic CE power-down
current – CMOS inputs
VCC = VCC(max),
IOUT = 0 mA
CMOS levels
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
µA
f = fmax (address and data only),
f = 0 (OE and WE) VCC = VCC(max)
ISB2
[7]
Automatic CE power-down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
2. VIL(min) = –2.0 V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
5. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. This parameter is guaranteed by design and not tested.
7. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95418 Rev. *D
Page 4 of 15
CY62148GN MoBL®
Capacitance
Parameter [8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [8]
Test Conditions
32-pin SOIC
Package
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
51.79
79.03
C/W
25.12
17.44
C/W
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
32-pin TSOP II Unit
Package
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms[9]
R1
VCC
OUTPUT
ALL INPUT PULSES
3.0 V
30 pF
INCLUDING
JIG AND
SCOPE
R2
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameter[8]
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800
R2
15385
1554
990
RTH
8000
645
639
VTH
1.20
1.75
1.77
V
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document Number: 001-95418 Rev. *D
Page 5 of 15
CY62148GN MoBL®
Data Retention Characteristics
Over the operating range
Parameter
Description
VDR
VCC for data retention
ICCDR[11, 12]
Data retention current
Conditions
VCC = 1.2V, CE > VCC – 0.2 V,
Min
Typ[10]
Max
Unit
1
–
–
V
–
–
13
µA
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR[13]
Chip deselect to data retention
time
0
–
–
ns
tR[13, 14]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.0 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. These parameters are guaranteed by design.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document Number: 001-95418 Rev. *D
Page 6 of 15
CY62148GN MoBL®
Switching Characteristics
Over the operating range
Parameter [15]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to low Z[16]
5
–
ns
–
18
ns
10
–
ns
–
18
ns
tHZOE
tLZCE
OE HIGH to high
CE LOW to low
Z[16, 17]
Z[16]
Z[16, 17]
tHZCE
CE HIGH to high
tPU
CE LOW to power-up
0
–
ns
CE HIGH to power-down
–
45
ns
tPD
Write
Cycle[18, 19]
tWC
Write cycle time
45
–
ns
tSCE
35
–
ns
tAW
CE LOW to write end
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
35
–
ns
tSD
WE pulse width
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
Z[16, 17]
–
18
ns
10
–
ns
tHZWE
WE LOW to high
tLZWE
WE HIGH to low Z[16]
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal wre.ite time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-95418 Rev. *D
Page 7 of 15
CY62148GN MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 25
tHD
DATA VALID
tHZOE
Notes
20. Device is continuously selected. OE, CE = VIL.
21. WE is HIGH for read cycles.
22. Address valid before or similar to CE transition LOW.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
25. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95418 Rev. *D
Page 8 of 15
CY62148GN MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (CE Controlled) [26, 27]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 29
tHD
DATA VALID
tHZWE
tLZWE
Notes
26. Data I/O is high impedance if OE = VIH.
27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
28. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
29. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95418 Rev. *D
Page 9 of 15
CY62148GN MoBL®
Truth Table
CE
H
WE
OE
[30]
I/O
Mode
Power
X
X
High Z
Deselect/power-down
Standby (ISB)
L
H
L
Data out
Read
Active (ICC)
L
L
X
Data in
Write
Active (ICC)
L
H
H
High Z
Selected, outputs disabled
Active (ICC)
Note
30. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95418 Rev. *D
Page 10 of 15
CY62148GN MoBL®
Ordering Information
Table 1. Key features and Ordering Information
Speed Voltage Range (V)
(ns)
45
2.2 V–3.6 V
4.5 V–5.5 V
Ordering Code
Package
Diagram
Package Type
CY62148GN30-45ZSXI
51-85095 32-pin TSOP II (Pb-free)
CY62148GN30-45ZSXIT
51-85095 32-pin TSOP II (Pb-free), Tape and Reel
CY62148GN30-45SXI
51-85081 32-pin SOIC (Pb-free)
CY62148GN30-45SXIT
51-85081 32-pin SOIC (Pb-free), Tape and Reel
CY62148GN-45ZSXI
51-85095 32-pin TSOP II (Pb-free)
CY62148GN-45ZSXIT
51-85095 32-pin TSOP II (Pb-free), Tape and Reel
CY62148GN-45SXI
51-85081 32-pin SOIC (Pb-free)
CY62148GN-45SXIT
51-85081 32-pin SOIC (Pb-free), Tape and Reel
Operating
Range
Industrial
Ordering Code Definitions
CY 621 4
8 GN XX - XX
XX X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or S
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns
Voltage Range: 30 = 3 V typ; no character = 5 V typ
Process Technology: GN = 65 nm
Bus width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-95418 Rev. *D
Page 11 of 15
CY62148GN MoBL®
Package Diagrams
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
51-85095 *D
Figure 10. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
51-85081 *E
Document Number: 001-95418 Rev. *D
Page 12 of 15
CY62148GN MoBL®
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 3. Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
Degrees Celsius
I/O
input/output
MHz
megahertz
OE
output enable
µA
microamperes
MoBL
More Battery Life
µs
microseconds
SOIC
small outline integrated circuit
mA
milliamperes
SRAM
static random access memory
TSOP
thin small outline package
WE
write enable
Document Number: 001-95418 Rev. *D
Symbol
Unit of Measure
ns
nanoseconds
ohms
%
percent
pF
picofarads
V
volts
W
watts
Page 13 of 15
CY62148GN MoBL®
Document History Page
Document Title: CY62148GN MoBL®, 4-Mbit (512K × 8) Static RAM
Document Number: 001-95418
Revision
ECN
Orig. of
Change
Submission
Date
**
5056496
NILE
12/29/2015
New data sheet.
*A
5092456
NILE
01/19/2016
Added “2.2 V to 3.6 V” range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
*B
5422041
NILE
09/09/2016
Updated Electrical Characteristics:
Changed minimum value of VOH parameter corresponding to “2.7 V to 3.6 V”
from 2.2 V to 2.4 V.
Changed minimum value of VIH parameter corresponding to “2.2 V to 2.7 V”
from 2.0 V to 1.8 V.
Updated Ordering Information:
Updated part numbers.
Updated Disclaimer.
Updated to new template.
*C
5546908
NILE
12/08/2016
Updated Ordering Information:
No change in part numbers.
Removed Disclaimer (text referencing to contact sales).
Completing Sunset Review.
*D
6002325
AESATMP9
12/21/2017
Updated logo and copyright.
Document Number: 001-95418 Rev. *D
Description of Change
Page 14 of 15
CY62148GN MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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cypress.com/iot
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Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
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© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product.In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95418 Rev. *D
Revised December 21, 2017
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