CY62157DV18L-70BVI

CY62157DV18 MoBL2 8M (512K x 16) Static RAM Features • • • • Very high speed: 55 ns and 70 ns Voltage range: 1.65V to 1.95V Pin compatible with CY62157CV18 Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 10 mA @ f = fMAX Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered in a 48-ball FBGA power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. • • • • • Functional Description[1] The CY62157DV18 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode reducing Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM ARRAY 2048 x 256 x 16 SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE OE BLE Power - down Circuit CE 2 CE 1 A11 A12 A13 A14 A15 A16 A17 A18 BHE BLE CE 2 CE 1 Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05126 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 17, 2003 CY62157DV18 MoBL2 Pin Configuration[2, 3] FBGA T op View 1 BLE I/O 8 I/O 9 VSS VCC I/O 14 I/O 15 A18 Notes: 2. NC pins are not connected to the die. 3. DNU pins are to be connected to VSS or left open. 2 OE B HE I/O 10 I/O 11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE 1 I/O 1 I/O 3 I/O 4 I/O 5 WE A11 6 CE 2 I/O 0 I/O 2 Vccq Vss q I/O 6 I/O 7 NC A B C D E F G H DNU I/O 12 I/O 13 NC A8 A14 A 12 A9 Document #: 38-05126 Rev. *B Page 2 of 10 CY62157DV18 MoBL2 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ......................... –0.2V to VCCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State[4] ....................................–0.2V to VCC + 0.2V DC Input Voltage[4] ................................ –0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature (TA) –40°C to +85°C Power Dissipation Operating, Icc (mA) VCC 1.65V to 1.95V Product Portfolio VCC Range(V) Product CY62157DV18L CY62157DV18LL Min. 1.65 1.65 Typ.[5] 1.8 1.8 Max. 1.95 1.95 Speed (ns) 55 70 55 70 f = 1 MHz Typ.[5] 1 1 Max. 5 5 10 8 10 8 f = fMAX Typ.[5] Max. 20 15 20 15 Standby, ISB2 (µA) Typ.[5] 2 2 2 2 Max. 20 20 5 5 DC Electrical Characteristics (Over the Operating Range) CY62157DV18-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled Vcc = 1.95V, IOUT = 0 mA, CMOS level Test Conditions IOH = −0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V 1.4 –0.2 –1 –1 10 1 2 2 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 20 5 20 5 1.4 –0.2 –1 –1 8 1 2 2 Typ.[5] Max. CY62157DV18-70 Min. 1.4 0.2 VCC + 0.2 0.4 +1 +1 15 5 20 5 µA Typ.[5] Max. Unit V V V V µA µA mA VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz ISB1 Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current – 0.2V, VIN > VCC − 0.2V, VIN LL < 0.2V, f = fMAX (Address CMOS Inputs and Data Only), f = 0 (OE, WE, BHE and BLE) Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current – 0.2V, VIN > VCC − 0.2V or LL VIN < 0.2V, f = 0, VCC = CMOS Inputs 1.95V ISB2 2 2 20 5 2 2 20 5 µA Capacitance[6] Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. 6 Unit pF pF COUT Output Capacitance 8 Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 6. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05126 Rev. *B Page 3 of 10 CY62157DV18 MoBL2 Thermal Resistance Parameter θJA θJC Description Thermal Resistance (Junction to Ambient)[6] Thermal Resistance (Junction to Case)[6] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W AC Test Loads and Waveforms R1 VCC OUTPUT GND CL = 30 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT R2 Rise Time: 1 V/ns Fall Time: 1 V/ns VCC Typ 10% ALL INPUT PULSES 90% 90% 10% THÉVENIN EQUIVALENT RTH V Parameters R1 R2 R TH VT H 1.8V 13500 10800 6000 0.80 UNIT Ω Ω Ω V Data Retention Characteristics Parameter VDR ICCDR tCDR[6] tR[7] Description VCC for Data Retention Data Retention Current VCC = 1.0V, CE1 > VCC – 0.2V, CE2 L < 0.2V, VIN > VCC − 0.2V or VIN < LL 0.2V 0 tRC Conditions Min. 1.0 1 Typ.[5] Max. 1.95 10 3 ns ns Unit V µA Chip Deselect to Data Retention Time Operation Recovery Time Data Retention Waveform[8] VCC CE1 or BHE . BLE or CE2 VCC(min.) tCDR DATA RETENTION MODE VDR > 1.0V VCC(min.) tR Notes: 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. . 8. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05126 Rev. *B Page 4 of 10 CY62157DV18 MoBL2 Switching Characteristics (Over the Operating Range)[9] CY62157DV18-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[11] tHZBE Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[10, 12] WE HIGH to Low Z[10] 10 55 45 45 0 0 45 45 25 0 20 10 70 60 60 0 0 50 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[10] OE HIGH to High Z[10, 12] CE1 LOW or CE2 HIGH to Low Z [10] CY62157DV18-70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 5 25 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. 55 Max. 55 10 55 25 5 20 10 20 0 55 55 5 20 CE1 HIGH or CE2 LOW to High Z[10, 12] CE1 LOW or CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[10] BLE/BHE HIGH to High-Z [10, 12] Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 11. If both byte enables are toggled together, this value is 10 ns. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL. 14. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 15. WE is HIGH for Read cycle. Document #: 38-05126 Rev. *B Page 5 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS t RC CE 1 t PD t HZCE tACE CE2 BHE /BLE t DBE t LZBE OE t HZBE t DOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE t LZCE tPU 50% DATA VALID t HZOE HIGH IMPEDANCE I CC I SB 50% Write Cycle No. 1 (WE Controlled) [13, 17, 18, 19] t WC ADDRESS tSCE CE1 CE2 tAW t SA WE t PWE t HA BHE /BLE tBW OE tSD DATA I/O DON’T CARE t HD DATA VALID IN t HZOE Notes: 16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. 17. Data I/O is high-impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05126 Rev. *B Page 6 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled) [13, 17, 18, 19] t WC ADDRESS t SCE CE 1 CE 2 t SA t AW t PWE t HA WE BHE /BLE t BW OE t SD DATA I/O DON’T CARE t HD DATA IN VALID t HZOE Write Cycle No. 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA I/O DON’T CARE tHA tPWE tHD DATAIN VALID tHZWE tLZWE Document #: 38-05126 Rev. *B Page 7 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19] t WC ADDRESS CE 1 CE 2 t SCE t AW t BW BHE /BLE t SA WE t PWE t SD DATA I/O DON’T CARE t HA t HD DATAIN VALID Truth Table CE 1 H X X L L L L L L L L L CE 2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Input / Outputs High Z High Z High Z Data Out I/O0– I/O15) ( Data Out I/O0– I/O7); ( High Z (I/O8– I/O15) High Z (I/O0– I/O7); Data Out I/O8– I/O15) ( High Z High Z High Z Data In (I/O0– I/O15) Data In (I/O0– I/O7); High Z (I/O8– I/O15) High Z (I/O0– I/O7); Data In (I/O8– I/O15) Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby(I SB ) Standby(I SB ) Standby(I SB ) Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Active CC) (I Ordering Information Speed (ns) 55 70 Ordering Code CY62157DV18L-55BVI CY62157DV18LL-55BVI CY62157DV18L-70BVI CY62157DV18LL-70BVI Package Name BV48A BV48A BV48A BV48A Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial Operating Range Industrial Document #: 38-05126 Rev. *B Page 8 of 10 CY62157DV18 MoBL2 Package Diagrams 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05126 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62157DV18 MoBL2 Document History Page Document Title: CY62157DV18 MoBL2 8M (512K x 16) Static RAM Document Number: 38-05126 REV. ** *A *B ECN NO. 112603 116601 124694 Issue Date 03/01/02 06/14/02 03/18/03 Orig. of Change GAV MGN DPM Description of Change New Data Sheet, Die rev replacing CY62157CV18 Added second power bin (L and LL) Changed from Advance Information to Preliminary Changed Preliminary to Final Added LL Bin to Iccdr = 3 uA max Added new footnotes (1 and 2) Filled in TBD values Document #: 38-05126 Rev. *B Page 10 of 10