CY62157DV30_06

CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL® Static RAM Features • Temperature Ranges — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • Very high speed: 45 ns • Wide voltage range: 2.20V–3.60V • Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 12 mA @ f = fmax • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball FBGA, 44-pin TSOPII, and Pb-free 48-pin TSOPI Functional Description[1] The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS 512K × 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE OE BLE A11 A12 A13 A14 A15 A16 A17 A18 CE2 CE1 Power-down Circuit Note: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05392 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 8, 2006 CY62157DV30 MoBL® Product Portfolio Power Dissipation Operating ICC, (mA) VCC Range (V) Product CY62157DV30L Range Industrial Min. 2.2 2.2 2.2 2.2 Typ.[2] 3.0 3.0 3.0 3.0 Max. 3.6 3.6 3.6 3.6 Speed (ns) 45, 55, 70 45, 55, 70 55 55 f = 1MHz Typ.[2] 1.5 1.5 1.5 1.5 Max. 3 3 3 3 f = fmax Typ.[2] 12 12 12 12 Max. 20 15 15 20 Standby ISB2, (µA) Typ.[2] 2 2 2 2 Max. 20 8 8 50 CY62157DV30LL Industrial CY62157DV30LL Automotive-A CY62157DV30L Automotive-E Pin Configuration[4, 5, 6] 48-Pin TSOP I Pinout Top View A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A19 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 48-Ball FBGA Pinout Top View 1 BLE I/O8 I/O9 VSS VCC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H 44-pin TSOP II Pinout Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O12 DNU A14 A12 A9 I/O14 I/O13 I/O15 A18 NC A8 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 3. NC pins are not internally connected on the die. 4. DNU pins have to be left floating. 5. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8 SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19, while BHE, BLE and I/O8 to I/O14 pins are not used. 6. The 44-TSOPII package device has only one chip enable pin (CE). Document #: 38-05392 Rev. *H Page 2 of 12 CY62157DV30 MoBL® Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential ............................................ –0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[8, 9] ............................ –0.3V to VCC(max) + 0.3V DC Input Voltage[8, 9] ........................–0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW) .............................20 mA Device CY62157DV30L CY62157DV30LL CY62157DV30LL Automotive-A –40°C to +85°C CY62157DV30L Automotive-E –40°C to +125°C Range Industrial Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Ambient Temperature (TA) –40°C to +85°C VCC[10] 2.20V to 3.60V Electrical Characteristics Over the Operating Range -45, -55, -70 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1 mA VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC Ind’l/Auto-A[7] Auto-E[7] IOZ GND < VO < VCC, Output Disabled Ind’l/Auto-A[7] Auto-E[7] VCC = VCCmax L IOUT = 0 mA LL CMOS levels L LL ISB1 Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current -CMOS Inputs L CE1 > VCC − 0.2V, CE2 < 0.2V Ind’l VIN > VCC – 0.2V, VIN < 0.2V) [7] LL f = fMAX (Address and Data Only), f = 0 Ind’l/Auto-A (OE, WE, BHE and BLE), VCC = 3.60V Auto-E[7] L CE1 > VCC– 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V Ind’l[7] L Ind’l/Auto-A[7] LL Auto-E[7] L Test Conditions VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 –0.3 –0.3 –1 –4 –1 –4 12 12 1.5 1.5 2 2 Min. Typ.[2] 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +4 +1 +4 20 15 3 3 20 8 50 2 2 20 8 50 µA Max. Unit V V V V V V V V µA µA µA µA mA mA mA mA µA ICC f = fMAX = 1/tRC f = 1 MHz ISB2 Capacitance[11, 12] Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 10 Unit pF pF COUT Output Capacitance 10 Notes: 7. Automotive-A and Automotive-E available only in -55. 8. VIL(min.) = –2.0V for pulse durations less than 20 ns. 9. VIH(max)= VCC+0.75V for pulse duration less than 20 ns. 10. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 11. Tested initially and after any design or process changes that may affect these parameters. 12. The input capacitance on the CE2 pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF. Document #: 38-05392 Rev. *H Page 3 of 12 CY62157DV30 MoBL® Thermal Resistance[11] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board FBGA 39.3 9.69 TSOP II 35.62 9.13 TSOP I 36.9 10.05 Unit °C/W °C/W AC Test Loads and Waveforms[13] R1 VCC OUTPUT 30 pF / 50 pF VCC GND R2 Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 2.50V 16667 15385 8000 1.20 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Parameters R1 R2 RTH VTH Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Ind’l (L) Ind’l/Auto-A (LL) Auto-E (L) 0 tRC Conditions Min. 1.5 10 4 25 ns ns Typ.[2] Max. Unit V µA tCDR [11] Chip Deselect to Data Retention Time Operation Recovery Time tR[14] Data Retention Waveform[15] VCC CE1 or BHE.BLE VCC, min. tCDR DATA RETENTION MODE VDR > 1.5 V VCC, min. tR or CE2 Notes: 13. Test condition for the 45 ns part is a load capacitance of 30 pF. 14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05392 Rev. *H Page 4 of 12 CY62157DV30 MoBL® Switching Characteristics Over the Operating Range [16] 45 ns[13] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [19] 55 ns Min. 55 Max. 70 ns Min. 70 55 70 10 55 25 70 35 5 20 25 10 20 25 0 55 55 70 70 10 20 25 70 60 60 0 0 45 60 30 0 20 25 10 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[17] OE HIGH to High Z [17, 18] [17] Min. 45 Max. 45 10 45 25 5 15 10 20 0 45 45 10 15 45 40 40 0 0 35 40 25 0 15 10 10 55 40 40 0 0 40 40 25 0 10 0 10 5 10 CE1 LOW and CE2 HIGH to Low Z CE1 HIGH and CE2 LOW to High Z[17, 18] CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH and CE2 LOW to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[17] BLE/BHE HIGH to HIGH Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[17, 18] WE HIGH to Low-Z [17] Z[17, 18] Notes: 15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 19. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05392 Rev. *H Page 5 of 12 CY62157DV30 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[20, 21] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle 2 (OE Controlled)[21, 22] ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE tLZOE HIGH IMPEDANCE tLZCE tPU SUPPLY CURRENT 50% 50% ICC ISB tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE DATA OUT DATA VALID Notes: 20. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 21. WE is HIGH for read cycle. 22. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05392 Rev. *H Page 6 of 12 CY62157DV30 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[19, 23, 24, 25] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tBW tPWE tHA BHE/BLE OE tSD DATA I/O See note 25 tHD VALID DATA tHZOE Write Cycle 2 (CE1 or CE2 Controlled)[19, 23, 24, 25] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA BHE/BLE OE tSD DATA I/O See note 25 tHD VALID DATA tHZOE Notes: 23. Data I/O is high-impedance if OE = VIH. 24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05392 Rev. *H Page 7 of 12 CY62157DV30 MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[24, 25] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tSA tPWE tHA WE tSD DATA I/O See note 25 tHD VALID DATA tHZWE tLZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25] tWC ADDRESS CE1 CE2 tSCE tAW tBW tHA BHE/BLE tSA WE tPWE tSD DATA I/O See note 25 tHD VALID DATA Document #: 38-05392 Rev. *H Page 8 of 12 CY62157DV30 MoBL® Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) Data Out (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data Out (I/O8–I/O15) High Z High Z High Z Data In (I/O0–I/O15) Data In (I/O0–I/O7); High Z (I/O8–I/O15) High Z (I/O0–I/O7); Data In (I/O8–I/O15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read (Upper byte and Lower Byte) Read (Lower Byte only) Read (Upper Byte only) Output Disabled Output Disabled Output Disabled Write (Upper byte and Lower Byte) Write (Lower Byte only) Write (Upper Byte only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05392 Rev. *H Page 9 of 12 CY62157DV30 MoBL® Ordering Information Speed (ns) 45 55 Ordering Code CY62157DV30L-45BVI CY62157DV30LL-45ZSXI CY62157DV30LL-55BVI CY62157DV30L-55BVXI CY62157DV30LL-55BVXI CY62157DV30L-55ZXI CY62157DV30LL-55ZSI CY62157DV30L-55ZSXI CY62157DV30LL-55ZSXI CY62157DV30LL-55BVXA CY62157DV30L-55BVXE CY62157DV30L-55ZSXE CY62157DV30LL-70BVI CY62157DV30LL-70BVXI Package Diagram 51-85150 51-85087 51-85150 Package Type 48-ball (6 x 8 x 1 mm) FBGA 44-pin TSOP II (Pb-free) 48-ball (6 x 8 x 1 mm) FBGA 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) 44-pin TSOP I (Pb-free) 44-pin TSOP II 44-pin TSOP II (Pb-free) 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) 44-pin TSOP II (Pb-free) 48-ball (6 x 8 x 1 mm) FBGA 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) Automotive-A Automotive-E Industrial Operating Range Industrial Industrial 51-85183 51-85087 70 51-85150 51-85150 51-85087 51-85150 Package Diagrams 48-ball FBGA (6 x 8 x 1 mm) (51-85150) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.00±0.10 8.00±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.00±0.10 A 1.875 0.75 3.75 B 6.00±0.10 0.55 MAX. 0.25 C 0.15(4X) 0.21±0.05 0.10 C 51-85150-*D SEATING PLANE 0.26 MAX. C 1.00 MAX Document #: 38-05392 Rev. *H Page 10 of 12 CY62157DV30 MoBL® Package Diagrams (continued) 48-pin TSOP I (12 mm x 18.4 mm x 1.0 mm) (51-85183) DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] 1 N 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0°-5° 0.002[0.05] 0.006[0.15] 51-85183-*A 44-pin TSOP II (51-85087) 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05392 Rev. *H Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62157DV30 MoBL® Document History Page Document Title: CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL® Static RAM Document Number: 38-05392 REV. ** *A *B *C ECN NO. Issue Date 126316 131013 133115 211601 05/22/03 11/19/03 01/24/04 See ECN Orig. of Change HRT CBD AJU Description of Change New Data Sheet Minor Change: Change MPN and upload. Change from Preliminary to Final Changed Marketing part number from CY62157DV to CY62157DV30 in the title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section CBD/LDZ Change from Advance to Preliminary *D *E *F *G 236628 257349 372074 433838 See ECN See ECN See ECN See ECN SYT/AJU Added 45-ns and 70-ns Speed Bins Added Automotive product information PCI SYT ZSD Added test condition for 45 ns part (footnote #13 on page 4) Added Pb-Free Automotive Part in the Ordering Information Removed ‘Preliminary’ tag from Automotive Information Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Updated the thermal resistance table Updated the ordering information table and changed the package name column to package diagram Added Automotive-A product Updated ordering Information table *H 488954 See ECN VKN Document #: 38-05392 Rev. *H Page 12 of 12