CY62157EV18LL-45BVXI

CY62157EV18 MoBL® 8-Mbit (512K x 16) Static RAM Features portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). • Very high speed: 45 ns • Wide voltage range: 1.65V–2.25V • Pin Compatible with CY62157DV18 and CY62157DV20 • Ultra-low standby power — Typical Standby current: 2µA — Maximum Standby current: 8µA • Ultra-low active power Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). — Typical active current: 1.8 mA @ f = 1 MHz • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in lead-free 48-ball VFBGA package Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. Functional Description[1] The CY62157EV18 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in Logic Block Diagram 512K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE CE2 CE1 OE BLE Power-Down Circuit BHE BLE CE2 CE1 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05490 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 17, 2006 CY62157EV18 MoBL® Pin Configuration[2] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 NC A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Product Portfolio Product CY62157EV18 Speed (ns) VCC Range (V) Min. Typ.[3] Max. 1.65 1.8 2.25 45 Power Dissipation Operating ICC, (mA) f = 1MHz Typ.[3] 1.8 f = fmax Standby, ISB2 (µA) Max. Typ.[3] Max. Typ.[3] Max. 3 18 25 2 8 Notes: 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05490 Rev. *B Page 2 of 11 CY62157EV18 MoBL® DC Input Voltage[4, 5] ......... –0.2V to 2.45V (VCCMAX + 0.2V) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ..............................–0.2V to 2.45V (VCCMAX + 0.2V) DC Voltage Applied to Outputs in High Z State[4, 5] ..............–0.2V to 2.45V (VCCMAX + 0.2V) Device Range Ambient Temperature CY62157EV18LL Industrial –40°C to +85°C VCC[6] 1.65V to 2.25V Electrical Characteristics Over the Operating Range 45 ns Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V VOL Output LOW Voltage VCC = 1.65V VIH Input HIGH Voltage VCC = 1.65V to 2.25V VIL Input LOW Voltage VCC = 1.65V to 2.25V IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz IOL = 0.1 mA Min. Typ.[3] Max. 1.4 Unit V 0.2 V 1.4 VCC + 0.2V V –0.2 0.4 V –1 +1 µA –1 +1 µA VCC = VCCmax IOUT = 0 mA CMOS levels 18 25 mA 1.8 3 mA ISB1 Automatic CE Power-Down Current — CMOS Inputs CE1 > VCC−0.2V or CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = VCC (max). 2 8 µA ISB2 Automatic CE Power-Down Current — CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = VCC (max). 2 8 µA Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = VCC(typ) 10 pF 10 pF Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. VIH(max.) = VCC + 0.5V for pulse durations less than 20 ns. 6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05490 Rev. *B Page 3 of 11 CY62157EV18 MoBL® Thermal Resistance Parameter Description ΘJA Thermal Resistance (Junction to Ambient)[7] ΘJC Thermal Resistance (Junction to Case)[7] Test Conditions BGA Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 72 °C/W 8.86 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT VCC 10% GND R2 Rise Time = 1 V/ns 30 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters Value Unit R1 13500 Ω R2 10800 Ω RTH 6000 Ω VTH 0.80 V Data Retention Characteristics[9] (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current VCC= VDR CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V tCDR[7] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time Min. Typ.[3] Max. 1.0 Unit V 1 3 µA 0 ns tRC ns Data Retention Waveform[9] VCC VCC,min. tCDR DATA RETENTION MODE VDR > 1.0 V VCC,min. tR CE1 or BHE.BLE or CE2 Note: 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05490 Rev. *B Page 4 of 11 CY62157EV18 MoBL® Switching Characteristics Over the Operating Range [10] 45 ns Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns 45 10 OE LOW to LOW Z[11] tHZOE OE HIGH to High Z[11, 12] tLZCE CE1 LOW and CE2 HIGH to Low Z[11] tLZOE ns 5 ns 18 10 Z[11, 12] ns ns ns ns tHZCE CE1 HIGH and CE2 LOW to High tPU CE1 LOW and CE2 HIGH to Power-Up tPD CE1 HIGH and CE2 LOW to Power-Down 45 ns tDBE BLE/BHE LOW to Data Valid 45 ns tLZBE[13] BLE/BHE LOW to Low Z[11] tHZBE BLE/BHE HIGH to HIGH 18 0 ns 5 Z[11, 12] ns ns 18 ns Write Cycle[14] tWC Write Cycle Time 45 ns tSCE CE1 LOW and CE2 HIGH to Write End 35 ns tAW Address Set-Up to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE/BHE LOW to Write End 35 ns tSD Data Set-Up to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High-Z[11, 12] WE HIGH to Low-Z[11] 18 10 ns ns Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. If both byte enables are toggled together, this value is 10 ns. 14. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05490 Rev. *B Page 5 of 11 CY62157EV18 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[16, 17] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 15. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05490 Rev. *B Page 6 of 11 CY62157EV18 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[14, 18, 19, 20] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA NOTE 20 tHZOE Write Cycle 2 (CE1 or CE2 Controlled)[14, 18, 19, 20] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA NOTE 20 tHZOE Notes: 18. Data I/O is high impedance if OE = VIH. 19. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 20. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05490 Rev. *B Page 7 of 11 CY62157EV18 MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[19, 20] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tPWE tSA WE tSD DATAI/O NOTE 20 tHD VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[19, 20] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 20 Document #: 38-05490 Rev. *B tHD VALID DATA Page 8 of 11 CY62157EV18 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X X H L H H L L H H L H L Mode Power High Z Deselect/Power-Down Standby (ISB) High Z Deselect/Power-Down Standby (ISB) H High Z Deselect/Power-Down Standby (ISB) L L Data Out (I/O0–I/O15) Read Active (ICC) L H L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) Document #: 38-05490 Rev. *B Inputs/Outputs Page 9 of 11 CY62157EV18 MoBL® Ordering Information Speed (ns) Ordering Code 45 CY62157EV18LL-45BVXI Package Diagram Operating Range Package Type 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial Please contact your local Cypress sales representative for availability of these parts Package Diagrams 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER 2 3 4 5 6 6 5 4 3 2 1 A B C C E F G D E F 2.625 8.00±0.10 D 0.75 A B 5.25 8.00±0.10 1 Ø0.30±0.05(48X) G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 0.15(4X) 51-85150-*D 1.00 MAX 0.26 MAX. SEATING PLANE C MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05490 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62157EV18 MoBL® Document History Page Document Title: CY62157EV18 MoBL® 8-Mbit (512K x 16) Static RAM Document Number:38-05490 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 202862 See ECN AJU New Data Sheet *A 291272 See ECN SYT Converted from Advance Information to Preliminary Changed VCC Max from 2.20 to 2.25 V Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs Changed ICCDR from 4 to 4.5 µA Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins Changed tDOE from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns Speed Bins respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns Speed Bins respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Added Lead-Free Package Information *B 444306 See ECN NXR Converted from Preliminary to Final. Removed 35 ns speed bin Removed “L” bin Changed ball E3 from DNU to NC Removed redundant footnote on DNU. Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to 2.45V Changed the ICC Typ. value from 16 mA to 18 mA and ICC Max. value from 28 mA to 25 mA for test condition f = fax = 1/tRC. Changed the ICC Max. value from 2.3 mA to 3 mA for test condition f = 1MHz. Changed the ISB1 and ISB2 Max. value from 4.5 µA to 8 µA and Typ. value from 0.9 µA to 2 µA respectively. Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF. Added Typ. value for ICCDR . Changed the ICCDR Max. value from 4.5 µA to 3 µA Corrected tR in Data Retention Characteristics from 100 µs to tRC ns Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tLZBE from 6 to 5 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Added footnote #13 Updated the ordering Information and replaced the Package Name column with Package Diagram. Document #: 38-05490 Rev. *B Page 11 of 11