CY62167DV30LL-45ZXI

CY62167DV30 MoBL® 16-Mbit (1M x 16) Static RAM Features • TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM • Very high speed: 45 ns • Wide voltage range: 2.2V – 3.6V • Ultra-low active power — Typical active current: 2 mA @ f = 1 MHz — Typical active current: 18.5 mA @ f = fMax (45 ns speed) • Ultra-low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball VFBGA and 48-pin TSOP I package also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. Functional Description[1] The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 1M × 16 / 2M x 8 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BYTE BHE WE OE BLE CE2 CE1 Power-Down Circuit A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE BLE CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05328 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 27, 2006 [+] [+] Feedback CY62167DV30 MoBL® Product Portfolio Power Dissipation Operating ICC(mA) VCC Range (V) Product CY62167DV30LL Min. 2.2 Typ.[2] 3.0 Max. 3.6 Speed (ns) 45 55 70 f = 1MHz Typ.[2] 2 Max. 4 f = fMax Typ.[2] 18.5 15 12 Max. 37 30 25 Standby ISB2(µA) Typ.[2] 2.5 Max. 22 Pin Configuration[3, 4, 5] 48-ball VFBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 DNU A B C D E F G H I/O12 DNU I/O13 A19 A8 A14 A12 A9 48-Pin TSOP I (Forward) (1M x 16/ 2M x 8)[6] Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 3. NC pins are not connected on the die. 4. DNU pins have to be left floating. 5. Ball H6 for the FBGA package can be used to upgrade to a 32M density. 6. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used (DNU). Document #: 38-05328 Rev. *G Page 2 of 12 [+] [+] Feedback CY62167DV30 MoBL® Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................–65°C to +150°C Ambient Temperature with Power Applied .............................................–55°C to +125°C Supply Voltage to Ground Potential ...... –0.2V to VCC + 0.3V DC Voltage Applied to Outputs in High-Z State[7, 8] ................................ –0.2V to VCC + 0.3V DC Input Voltage[7, 8] ............................. –0.2V to VCC + 0.3V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .....................................................> 200 mA Operating Range Device Range Ambient Temperature –40°C to +85°C VCC[9] 2.20V to 3.60V CY62167DV30LL Industrial Electrical Characteristics Over the Operating Range CY62167DV30-45 CY62167DV30-55 CY62167DV30-70 Parameter Description VOH Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 –0.3 VCC 1.8 +0.3V 2.2 0.6 0.8 –1 +1 +1 –1 –1 –0.3 VCC 1.8 +0.3V 2.2 0.6 0.8 +1 +1 –1 –1 –0.3 VCC +0.3V 0.6 0.8 +1 +1 µA µA V Min. Typ.[2] Max. Min. Typ.[2] Max. Min. Typ.[2] Max. Unit 2.0 2.4 0.4 2.0 2.4 0.4 2.0 2.4 0.4 V V VOL VIH VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VIL V IIX IOZ Input Leakage GND < VI < VCC Current Output Leakage Current GND < VO < VCC, Output Disabled –1 ICC VCC Operating VCC = VCC(max) IOUT = 0 mA Supply CMOS levels Current Automatic CE Power-down Current — CMOS Inputs f = fMax = 1/tRC f = 1 MHz 18.5 2 2.5 37 4 22 15 2 2.5 30 4 22 12 2 2.5 25 4 22 mA ISB1 CE1 > VCC − 0.2V or CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V, f = fMax (Address and Data Only), f = 0 (OE, WE, BHE, BLE), VCC = 3.60V CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V µA ISB2 Automatic CE Power-down Current — CMOS Inputs 2.5 22 2.5 22 2.5 22 µA Notes: 7. VIL(min.) = –2.0V for pulse durations less than 20 ns. 8. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 9. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) and VCC must be stable at VCC(min) for 500 µs. Document #: 38-05328 Rev. *G Page 3 of 12 [+] [+] Feedback CY62167DV30 MoBL® Capacitance[10, 11] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. 8 10 Unit pF pF Thermal Resistance[10] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, 2-layer printed circuit board VFBGA 55 16 TSOP I 60 4.3 Unit °C/W °C/W AC Test Loads and Waveforms[12] VCC OUTPUT 50 pF[12] INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V R1 VCC R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Parameters R1 R2 RTH VTH 2.5V 16667 15385 8000 1.20 3.0V 1103 1554 645 1.75 Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 10 Typ.[2] Max. Unit V µA tCDR[10] tR[13] Chip Deselect to Data Retention Time Operation Recovery Time ns ns Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. This applies for all packages. 12. Test condition for the 45 ns part is with a load capacitance of 30 pF. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05328 Rev. *G Page 4 of 12 [+] [+] Feedback CY62167DV30 MoBL® Data Retention Waveform[14] VCC CE1 or BHE,BLE VCC, min. tCDR DATA RETENTION MODE VDR > 1.5 V VCC, min. tR or CE2 Switching Characteristics Over the Operating Range[15] 45 ns [12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE [18] 55 ns Min. 55 Max. 70 ns Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 10 25 70 60 60 0 0 45 60 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 10 ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[16] OE HIGH to High Z[16, 17] Z[16] CE1 LOW and CE2 HIGH to Low Min. 45 Max. 45 10 45 25 5 15 10 20 0 45 45 10 15 45 40 40 0 0 35 40 25 0 15 10 10 55 40 40 0 0 40 40 25 0 10 0 10 5 10 55 55 25 20 20 55 55 20 CE1 HIGH and CE2 LOW to High Z[16, 17] CE1 LOW and CE2 HIGH to Power-up CE1 HIGH and CE2 LOW to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[16] BLE/BHE HIGH to HIGH Z[16, 17] Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[16, 17] WE HIGH to Low-Z[16] 20 Notes: 14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 15. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05328 Rev. *G Page 5 of 12 [+] Feedback CY62167DV30 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[19, 20] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle 2 (OE Controlled)[20, 21] ADDRESS CE1 tRC tPD CE2 BHE/BLE tLZBE tDBE tHZBE tHZCE tACE OE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU tDOE DATA VALID tHZOE HIGH IMPEDANCE ICC ISB 50% 50% Notes: 19. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05328 Rev. *G Page 6 of 12 [+] [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[18, 22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tBW tPWE tHA BHE/BLE OE tSD DATA I/O See Note 23 tHD VALID DATA tHZOE Notes: 22. Data I/O is high-impedance if OE = VIH. 23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 24. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05328 Rev. *G Page 7 of 12 [+] [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 2 (CE1 or CE2 Controlled)[18, 22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA BHE/BLE OE tSD DATA I/O See Note 23 tHD VALID DATA tHZOE Write Cycle 3 (WE Controlled, OE LOW)[23, 24] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tHA tPWE WE tSA tSD DATA I/O See Note 23 tHD VALID DATA tHZWE tLZWE Document #: 38-05328 Rev. *G Page 8 of 12 [+] [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW)[23, 24] tWC ADDRESS CE1 CE2 tAW tBW BHE/BLE tSA WE tPWE tSD DATA I/O See Note 23 tSCE tHA tHD VALID DATA Truth Table CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H L L L H H H OE X X X L L L X X X H H H BHE X X H L H L L H L L H L BLE X X H L L H L L H H L L Inputs/Outputs High Z High Z High Z Data Out (I/O0–I/O15) High Z (I/O8–I/O15); Data Out (I/O0–I/O7) Data Out (I/O8–I/O15); High Z (I/O0–I/O7) Data In (I/O0–I/O15) High Z (I/O8–I/O15); Data In (I/O0–I/O7) Data In (I/O8–I/O15); High Z (I/O0–I/O7) High Z High Z High Z Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05328 Rev. *G Page 9 of 12 [+] [+] Feedback CY62167DV30 MoBL® Ordering Information Speed (ns) 45 55 Ordering Code CY62167DV30LL-45ZXI CY62167DV30LL-55BVI CY62167DV30LL-55BVXI CY62167DV30LL-55ZI CY62167DV30LL-55ZXI CY62167DV30LL-70BVI Package Package Type Diagram 51-85183 48-pin TSOP I (12 x 18.4 x 1 mm) (Pb-free) 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) 51-85183 48-pin TSOP I (12 x 18.4 x 1 mm) 48-pin TSOP I (12 x 18.4 x 1 mm) (Pb-free) 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) Operating Range Industrial 70 Please contact your local Cypress sales representative for availability of these parts Package Diagrams 48-ball VFBGA (8 x 9.5 x 1 mm) (51-85178) TOP VIEW BOTTOM VIEW Ø0.05 M C Ø0.25 M C A B A1 CORNER A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 9.50±0.10 9.50±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 8.00±0.10 A 1.875 0.75 3.75 0.55 MAX. 0.25 C B 0.21±0.05 0.10 C 0.15(4X) 8.00±0.10 SEATING PLANE 0.26 MAX. C 1.00 MAX 51-85178-** Document #: 38-05328 Rev. *G Page 10 of 12 [+] [+] Feedback CY62167DV30 MoBL® Package Diagrams (continued) 48-pin TSOP I (12 x 18.4 x 1mm) (51-85183) DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] 1 N 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0.002[0.05] 0.006[0.15] 0°-5° 51-85183-*A MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05328 Rev. *G Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY62167DV30 MoBL® Document History Page Document Title: CY62167DV30 MoBL®, 16-Mbit (1M x 16) Static RAM Document Number: 38-05328 REV. ** *A *B *C *D *E *F ECN NO. Issue Date 118408 123692 126555 127841 205701 238050 304054 See ECN See ECN 09/30/02 02/11/03 04/25/03 09/10/03 Orig. of Change GUG DPM DPM XRJ AJU New Data Sheet Changed Advanced to Preliminary Added package diagram Minor change: Changed Sunset Owner from DPM to HRT Added 48 TSOP I package Changed BYTE pin usage description for 48 TSOPI package Description of Change KKV/AJU Replaced 48-ball VFBGA package diagram; Modified Package Name in Ordering Information table from BV48A to BV48B PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #12 on page #4 Added Pb-free packages on page # 10 Modified datasheet to explain x8 configurability Removed L power bin from the product offering Updated Ordering Information Table *G 492895 See ECN VKN Document #: 38-05328 Rev. *G Page 12 of 12 [+] [+] Feedback